(en)A voltage or current regulated power converter for charging batteries, is described. The power converter comprises an inductor (L), a capacitor cell (C 1 , C 2 ), switches (S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8 ) and a controller. The controller controls the switches such that a commutation cycle of the power converter comprises a first phase, during which the capacitor cell and the inductor are arranged in series and during which a voltage across the serial arrangement of the capacitor cell and the inductor corresponds to V in −V out ; a second phase, during which the capacitor cell and the inductor are arranged in series and during which the voltage across the serial arrangement of the capacitor cell and the inductor corresponds to −V out ; and a third phase, during which the capacitor cell is floating and during which the voltage across the inductor corresponds to V in −V out or to −V out .

1.ApplicationNumber: US-201514966003-A
1.PublishNumber: US-2016344214-A1
2.Date Publish: 20161124
3.Inventor: PETERSEN HOLGER
MACRI NICOLA

4.Inventor Harmonized: PETERSEN HOLGER(DE)
MACRI NICOLA(DE)

5.Country: US
6.Claims:
(en)A voltage or current regulated power converter for charging batteries, is described. The power converter comprises an inductor (L), a capacitor cell (C 1 , C 2 ), switches (S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8 ) and a controller. The controller controls the switches such that a commutation cycle of the power converter comprises a first phase, during which the capacitor cell and the inductor are arranged in series and during which a voltage across the serial arrangement of the capacitor cell and the inductor corresponds to V in −V out ; a second phase, during which the capacitor cell and the inductor are arranged in series and during which the voltage across the serial arrangement of the capacitor cell and the inductor corresponds to −V out ; and a third phase, during which the capacitor cell is floating and during which the voltage across the inductor corresponds to V in −V out or to −V out .

7.Description:
(en)TECHNICAL FIELD
The present document relates to power converters with regulated output voltage or output current. In particular, the present document relates to switched power converters for charging applications.
BACKGROUND
The efficiency of a conventional switched power converter, such as a buck converter, is dominated by the losses within the switches (e.g. field effect transistors, FETs) and the inductor of the power converter. If the power converter is supplied from a relatively high input voltage Vin, the power converter typically exhibits a reduced conversion efficiency, because the switches must be implemented in high voltage technology, and thus the switches have an increased switch area and increased reverse recovery losses. Relatively large FETs typically cause relatively high switching losses, because of an increased gate charge and LX capacitance.
The voltage which is applied to the inductor of a buck converter is proportional to the difference between the input voltage V in and the output voltage V out , i.e. V in −V out , during the magnetization phase, or proportional to −V out during the demagnetization phase. Increased inductor voltages cause increased current variations dI/dt and thus an increased switching frequency (for achieving a pre-determined current ripple) and/or an increased current ripple (for a given switching frequency). In both cases this leads to increased inductor core losses and to an increased dissipation power.
Maintaining low current variations dI L /dt at increased input and output voltages typically requires inductors (i.e. coils) with increased inductance L, due to the relation dI L /dt=V L /L. However coils with an increased inductance L have an increased number of turns. For inductors to maintain their Direct Current Resistance (DCR) even with an increased number of turns, each turn has to make use of a wire with an increased thickness to compensate for the impedance increase. Thus the size of the inductor is growing twice with an increased inductance L (due to the increased number of turns and due to the increased wire thickness). On the other hand, if the inductor dimensions are not increased, an increased inductance L leads to the effect that the DCR of the inductor is growing twice due to the additional number of turns and due to the use of a thinner wire.
Over the last years battery powered applications (like smartphones and tablets) increased their computing power, screen resolution and display frame rate and added connected standby modes. This caused an increased drain of the battery of such devices, so that electronic devices such as smartphones typically need to be re-charged on a daily basis. The limited mobility time of battery powered electronic devices may be addressed by using battery packs with an increased capacity, but a re-charge of such battery packs requires relatively long time intervals. This is caused by the fact that most of the electronic devices are charged through a standard (Micro) USB port, which provides limited current handling capability (˜1.5 A). Therefore a 5 Ah battery pack requires multiple hours for re-charging, even if the battery technology (typically Lilon/LiPolymer) would allow a re-charge within less than one hour (1-2 C charging).
Recent changes in the USB charging specification allow voltages higher than the standard 5V, enabling more than four times the power from the USB supply (9V, 12V and 20V). However, due to the fact that electronic devices are space and height constrained (especially regarding the inductors used for switched power converters), an increased input voltage V in of a power converter (provided e.g. via the USB port) cannot be compensated by using inductors of higher inductance L. As a result of this, either the DCR of the inductor is increased or the switching frequency has to be increased. Both measures lead to an increased dissipation power and possibly hot spots at the housing of an electronic device.
SUMMARY
The present document addresses the above mentioned technical problem. In particular, the present document addresses the technical problem of providing a power converter for relatively high input voltages and/or for relatively high conversion ratios, with reduced size and with reduced power dissipation. According to an aspect, a power converter (notably a switched power converter) configured to derive electrical power at an output voltage V out at the output of the power converter from electrical power at an input voltage V in at the input of the power converter is described. The input and the output of the power converter typically comprise a positive and a negative contact, respectively. The input voltage may correspond to the voltage between the positive contact and the negative contact at the input. The output voltage may correspond to the voltage between the positive contact and the negative contact at the output. The power converter may be particularly adapted to charge a battery. In particular, the power converter may be adapted to provide a substantially constant charging current (e.g. the reference current I ref ) to a battery. The power converter comprises an inductor (also referred to as a coil) and a capacitor cell (comprising a capacitor or corresponding to a capacitor or comprising a capacitive voltage divider), a plurality of switches (each comprising e.g. one or more metaloxide semiconductor transistors) and a controller (comprising e.g. a processor).
The controller is configured to control the plurality of switches such that a commutation cycle of the power converter comprises a first phase, during which the capacitor cell and the inductor are arranged in series. Furthermore, during the first phase a magnitude of a voltage across the serial arrangement of the capacitor cell and the inductor corresponds to the magnitude of (V in −V out ). In particular, the voltage across the serial arrangement of the capacitor cell and the inductor may correspond to V in −V out . In other words, during the first phase, the serial arrangement of the capacitor cell and the inductor may be arranged between the input voltage (and the input of the power converter) on one side and the output voltage (and the output of the power converter) on the other side. As a result of this, the capacitor cell may be charged during the first phase.
Furthermore, the controller is configured to control the plurality of switches such that the commutation cycle of the power converter comprises a second phase, during which the capacitor cell and the inductor are arranged in series. Furthermore, during the second phase the magnitude of the voltage across the serial arrangement of the capacitor cell and the inductor corresponds to the magnitude of V out . In particular, the voltage across the serial arrangement of the capacitor cell and the inductor may correspond to −V out . In other words, the serial arrangement of the capacitor cell and the inductor may be arranged in parallel to the output voltage (and to the output of the power converter). As a result of this, the capacitor cell may be discharged during the second phase.
In addition, the controller is configured to control the plurality of switches such that the commutation cycle of the power converter comprises a third phase, during which the capacitor cell is decoupled from the output of the power converter (e.g. the capacitor cell may be floating). During the third phase the magnitude of the voltage across the inductor may correspond to the magnitude of (V in −V out ) or to the magnitude of V out . In particular, the voltage across the inductor may correspond to V in −V out or to −V out . As such, the third phase may comprise a first variant during which the inductor is coupled to the input voltage (on one side of the inductor) and to the output voltage (on the other side of the inductor) and a second variant during which the inductor is coupled to ground and to the output voltage, i.e. during which the inductor is arranged in parallel to the output of the power converter.
The output voltage may be regulated to a predetermined reference voltage, e.g. V ref =V in /2. V out can be any voltage smaller than V in , but the controller typically regulates the duty cycle of the first and second phase such that the voltage over the capacitor V c across the capacitor cell is ˜V in /2. Highest converter efficiency can typically be achieved for V out =V c =V in /2). The controller may be configured to set the duration of the first, second and third phase during a commutation cycle (i.e. the duty cycle), such that the output voltage of the power converter is regulated to the predetermined reference voltage V ref .
The third phase may be used to regulate the (average) output current of the power converter to a pre-determined reference current I ref . For this purpose, the output current of the power converter may be sensed using current sensing means, wherein the current sensing means may make use of current sensing technologies such as matched filters and/or current mirroring. The output current at the end of the first and/or second phase may be sensed. In particular, the cumulated and/or average output current at the end of the first and/or second phase may be sensed. Furthermore, it may be determined whether the (cumulated/average) output current at the end of the first and/or second phase is greater than or smaller than the pre-determined reference current I ref . Depending on this comparison, the first or the second variant may be used for a third phase that follows the first and/or the second phase. In particular, the first variant may be used if the output current is below the pre-determined reference current I ref and the second variant may be used if the output current is above the pre-determined reference current I ref .
The controller may be configured to set a duration of the third phase such that at the end of the third phase, the (average) output current is equal to or greater than the reference current I ref , notably if the (average) output current I out at the end of the first phase and/or at the end of the second phase is smaller than the reference current I ref . Alternatively or in addition, the controller may be configured to set a duration of the third phase such that at the end of the third phase, the (average) output current I out is equal to or smaller than the reference current I ref , notably if the (average) output current I out at the end of the first phase and/or at the end of the second phase is greater than the reference current I ref . By doing this, a precise regulation of the output current may be achieved.
The power converter enables the use of relatively small inductors. Furthermore, the power converter enables a reduction of the voltage variations across the inductor. Hence, the power converter allows the reduction of the size of the power converter and of the power dissipation of the power converter.
The controller may be configured to control the plurality of switches such that within a commutation cycle subsequent to the first phase and/or subsequent to the second phase, the power converter is operated in the third phase. By inserting the third phase subsequent to the first phase and subsequent to the second phase, the input voltage ripple may be reduced.
The controller may be configured to set a duty cycle of a commutation cycle such that the input voltage V in is greater or equal to 2V out . In particular, the duty cycle of a commutation cycle may be controlled such that the output voltage corresponds (in average) to the reference voltage V ref , e.g. half of the input voltage. The duty cycle may correspond to or may depend on the ratio of the duration of the first phase and the duration of a complete commutation cycle which comprises the first phase, the second phase and possibly one or more third phases.
The power converter may comprise a first sub-converter comprising a first plurality of switches (e.g. a subset of the total plurality of switches) and a first capacitor cell (e.g. a first capacitor). Furthermore, the power converter may comprise a second sub-converter comprising a second plurality of switches (e.g. a subset of the total plurality of switches) and a second capacitor cell (e.g. a second capacitor).
The first and second sub-converters may be operated in an interleaved manner, thereby reducing the ripple of the input voltage/input current. In particular, the controller may be configured to control the first and second pluralities of switches such that the first and second sub-converters are operated in an interleaved manner. The interleaved operation may be such that during the first phase, the second capacitor cell is discharged, that during the second phase, the first capacitor cell is discharged, and that during the third phase, the first capacitor cell and the second capacitor cell are decoupled from the output (e.g. floating). Furthermore, during the first phase, the first capacitor cell may be charged and during the second phase, the second capacitor cell may be charged (as illustrated e.g. in the example shown in FIG. 1 b ). Alternatively, the first and second capacitor cells may be continuously charged during the first and second phases with the same current (as illustrated e.g. in the example shown in FIG. 4 a ).
Furthermore, the controller may be configured to control the first and second pluralities of switches such that during the first phase and during the second phase, the first capacitor cell is arranged in series with the inductor and the second capacitor cell is arranged in series with the inductor. As such, the current through the inductor is provided by the first and the second capacitor cell. As such, the power converter may comprise only a single inductor for the first sub-converter and for the second sub-converter. By doing this, the size of the power converter may be further reduced.
The first plurality of switches may comprise a first switch configured to (directly) couple a first side of the first capacitor cell to the input voltage, a second switch configured to (directly) couple the first side of the first capacitor cell to the inductor, a third switch configured to (directly) couple a second side of the first capacitor cell to the inductor, and a fourth switch configured to (directly) couple the second side of the first capacitor cell to ground. Furthermore, the second plurality of switches may comprise an 8 th switch configured to (directly) couple a first side of the second capacitor cell to the input voltage, a 7 th switch configured to (directly) couple the first side of the second capacitor cell to the inductor, a 6 th switch configured to (directly) couple a second side of the second capacitor cell to the inductor, and a 5 th switch configured to (directly) couple the second side of the second capacitor cell to ground.
Alternatively, the first and the second capacitor cells may be arranged in series between the positive contact and the negative contact of the input of the power converter. A first end of the first capacitor cell may be coupled to the positive contact of the input of the power converter, a second end of the first capacitor cell may be coupled to a first end of the second capacitor cell, and a second end of the second capacitor cell may be coupled to the negative contact of the input of the power converter. The plurality of switches may comprise a first switch configured to (directly) couple the second end of the first capacitor cell to the inductor, a second switch configured to (directly) couple the second end of the first capacitor cell to ground and/or the negative contact of the output of the power converter, a third switch configured to (directly) couple the second end of the second capacitor cell to the negative contact of the output of the power converter, and a fourth switch configured to (directly) couple the first end of the first capacitor cell to the inductor. As such, an interleaved operation of two sub-converters may be implemented with a reduced number of switches, thereby reducing the size and power dissipation of the power converter. In particular, the two sub-converters, which comprise the two capacitor cells respectively, make use at least partially of and/or may comprise at least partially the same switches.
The power converter may comprise a first inductor and a second inductor. The controller may be configured to control the plurality of switches such that during a first fraction of the first phase and a first fraction of the second phase, the capacitor cell is arranged in series with the first inductor, while the second inductor is coupled to ground. Furthermore, the controller may be configured to control the plurality of switches such that during a second fraction of the first phase and a second fraction of the second phase, the capacitor cell is arranged in series with the second inductor, while the first inductor is coupled to ground. Furthermore, during a further fraction of the first phase and/or the second phase, the first inductor and the second inductor may be arranged in parallel to one another and in series with the capacitor cell. By splitting up the inductor into a first inductor and a second inductor, the conversion efficiency of the power converter may be further increased.
As indicated above, a capacitor cell may comprise a single capacitor. Alternatively, a capacitor cell may comprise a capacitive voltage divider, e.g. a Dickson voltage divider, comprising a plurality of capacitors. By doing this, various different reference voltages V ref for the output voltage, e.g. V ref =2V in /3, V in /3, V in /4, etc., may be provided. The reference voltage V ref indicates the output voltage for which the different power converters operate with optimum efficiency. Furthermore, the reference voltage V ref indicates the output voltage, at which the third phase of operation of the power converter typically changes from a first variant to a second variant or vice versa.
An inductance L of the inductor measured in Henrys may be smaller than the capacitance C of the capacitor measured in Farads by at least one or two orders of magnitude. As such, a small sized, power efficient power converter may be provided.
According to a further aspect, a cascaded power converter is described. The cascaded power converter comprises a power converter as described in the present document. Furthermore, the cascaded power converter comprises a capacitive voltage divider stage configured to derive the input voltage for the power converter from a global input voltage, wherein the global input voltage is greater than the input voltage. A commutation cycle of the capacitive voltage divider stage may be synchronized with a commutation cycle of the power converter. Furthermore, a frequency of the commutation cycle of the capacitive voltage divider stage may be k times smaller than a frequency of the commutation cycle of the power converter, with k being a positive integer. By using a cascaded power converter, the power efficiency of a power converter may be optimized for conversion ratios of 0.25 and below.
According to another aspect, a method for operating a controller of a power converter as outlined in the present document is described. The method may comprise steps which correspond to the features of the controller and power converter described in the present document. The method is directed at controlling the switches of a power converter, wherein the power converter is configured to derive electrical power at an output voltage V out from electrical power at an input voltage V in , wherein the power converter comprises an inductor and a capacitor cell and a plurality of switches. The method comprises controlling the plurality of switches such that a commutation cycle of the power converter comprises a first phase, during which the capacitor cell and the inductor are arranged in series and during which a voltage across the serial arrangement of the capacitor cell and the inductor corresponds to V in −V out . Furthermore, the method comprises controlling the plurality of switches such that the commutation cycle of the power converter comprises a second phase, during which the capacitor cell and the inductor are arranged in series and during which the voltage across the serial arrangement of the capacitor cell and the inductor corresponds to −V out . In addition, the method comprises controlling the plurality of switches such that the commutation cycle of the power converter comprises a third phase, during which the capacitor cell is floating and during which the voltage across the inductor corresponds to V in −V out or to −V out .
According to a further aspect, a software program is described. The software program may be adapted for execution on a processor and for performing the method steps outlined in the present document when carried out on the processor.
According to another aspect, a storage medium is described. The storage medium may comprise a software program adapted for execution on a processor and for performing the method steps outlined in the present document when carried out on the processor.
According to a further aspect, a computer program product is described. The computer program may comprise executable instructions for performing the method steps outlined in the present document when executed on a computer.
It should be noted that the methods and systems including its preferred embodiments as outlined in the present document may be used stand-alone or in combination with the other methods and systems disclosed in this document. In addition, the features outlined in the context of a system are also applicable to a corresponding method. Furthermore, all aspects of the methods and systems outlined in the present document may be arbitrarily combined. In particular, the features of the claims may be combined with one another in an arbitrary manner.
In the present document, the term “couple” or “coupled” refers to elements being in electrical communication with each other, whether directly connected e.g., via wires, or in some other manner.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention is explained below in an exemplary manner with reference to the accompanying drawings, wherein
FIGS. 1 a and 1 b illustrate example power converters;
FIGS. 2 a and 2 b illustrate example voltages and currents at a power converter;
FIGS. 3 a to 3 e illustrate example operation phases of a power converter;
FIGS. 4 a to 4 f illustrate further example power converters;
FIG. 5 illustrates a further example power converter; and
FIG. 6 shows a flow chart of an example method for controlling a power converter.



DESCRIPTION
As outlined above, the present document addresses the technical problem of providing power converters which are configured to cope with an increased input voltage V in and/or an increased input power, and which nonetheless have a limited size and limited power dissipation.
In particular, the present document is directed at increasing battery charging conversion efficiency (wired or wireless) to >93% in order to reduce dissipation power to a range that can be handled without overheating an electronic device. In this context, the negative impact on the efficiency caused by charger supply voltages that are significantly higher than the battery pack voltage is addressed. The challenge here is to operate within the space constraints of a target electronic device, which typically requires the use of relatively small inductors. Furthermore, the input voltage ripple which is due to relatively low switching frequencies should be reduced for limited ringing and EMI emission from the wires to the power supply of the electronic device.
As indicated above, the present document is particularly focused on battery charging. It should be noted, however, that the disclosure of the present document also applies to all applications that require DC-DC step buck type conversion at high efficiency, notably if, because of space constraints, low switching frequency cannot be achieved through high inductance coils.
A possibility to cope with an increased input voltage is to make use of a cascaded number of buck converters. However, the efficiencies of cascaded stages are multiplied, which results in a reduced overall efficiency in addition to a cost and area overhead. The drawbacks of cascaded converters can be reduced by using unregulated switched capacitor voltage division within at least one of the stages, as capacitors are much smaller than inductors with similar energy storage capacity and the conversion efficiency can be up to 98-99%. A limitation of cascaded buck converters is the maximum conversion ratio, which is always less than the conversion ratio of each stage. So in case of switched capacitive division, the maximum conversion ratio of the overall regulator is less than the conversion ratio of the divider cell (e.g. conversion ration D<0.5, when using a 2:1 capacitive divider stage). This disables the usage of cascaded converters for certain applications.
A further possibility is the use of multi-level buck converters. A multi-level buck converter typically requires twice the amount of switches than a standard buck converter. However, at least the bottom and mid switches (relative to ground) of a multi-level buck converter are not exposed to voltages higher than V in /2, which enables the usage of FETs with reduced voltage ratings, providing lower on-resistances R dson at similar parasitic capacitance and reduced reverse recovery loss. The reduced switching frequency of a multi-level buck converter improves the efficiency, but the duration of time intervals, when there's no current drawn from the input is extended. For a 2:1 conversion ratio the full output current is pulled from the input rail at a duty cycle of ˜50%. In case of a USB charger this increases the input voltage ripple, because the maximum termination capacitance is restricted by the USB specifications.
FIG. 1 a shows an interleaved 3-level buck converter 100 . The interleaved 3-level buck converter 100 comprises two instances or two sub-converters 110 , 120 of a 3-level buck converter 100 which are operated in an interleaved manner, thereby reducing the input voltage ripple. The structure of FIG. 1 a can be compacted (see FIG. 1 b ) by making use of a single inductor 104 , instead of the separate inductors 112 , 122 for the instances 112 , 120 , respectively, thereby reducing the size of the interleaved 3-level buck converter 150 , compared to the interleaved 3-level buck converter 100 .
The power converter 150 of FIG. 1 b reduces input voltage ripple caused by limited input capacitance at low switching frequency. Furthermore, the power converter 150 requires only a single inductor 104 .
FIG. 2 a shows an example input voltage V in 201 , inductor current I L1 202 , capacitor voltage V C1 203 at the capacitor C 1 111 , output current I out 204 , output voltage V out 205 and the control voltage 206 for the switches of the converter 110 . FIG. 2 b shows an example input voltage V in 201 , inductor current I L 202 , capacitor voltage V C1 203 at the capacitor C 1 111 , output current I out 204 , output voltage V out 205 and the control voltage 206 for the switches of the converter 150 . It can be seen that using the same total switch area, the voltage ripple of the input voltage 201 can be reduced to less than 10%, when using the converter 150 . Furthermore, a symmetric shape of the inductor current ripple can be achieved when using the converter 150 . In contrast to this, the inductor current signal of FIG. 2 a is slightly different for consecutive switching cycles. This results from the fact that one of the inductor demagnetizing phases is discharging in parallel to the switching capacitor, with the consecutive inductor demagnetizing phase charging the switching capacitance at the same time.
The power converter 150 comprises a control circuit (not shown), which is configured to control the switches S 1 through S 8 of the power converter 150 . In particular, the switches may be operated such that the power converter 150 is put successively into different phases. Example phases are illustrated in the FIGS. 3 a through 3 e.
In a first phase which is illustrated in FIG. 3 a all odd switches S 1 , S 3 , S 5 and S 7 are closed (whereas the even switches S 2 , S 4 , S 6 and S 8 are open). The first phase ramps the inductor current I L while charging the flying capacitor C 1 from I in and discharging the flying capacitor C 2 in parallel.
In a second phase which is illustrated in FIG. 3 b all odd switches S 1 , S 3 , S 5 and S 7 are open, whereas the even switches S 2 , S 4 , S 6 and S 8 are closed. The second phase ramps the inductor current I L while charging the flying capacitor C 2 from I in and discharging the flying capacitor C 1 in parallel.
The duration of the first and/or the second phase may be controlled in a way so that the charge of both flying capacitors C 1 and C 2 is balanced. In case of a constant output current, this condition triggers an identical duration of the first phase and the second phase.
Furthermore, the multi-level buck converter 150 is operated in a 3 rd phase for balancing the current in the inductor L after having finished the charging and discharging of the flying capacitor network C 1 , C 2 . For a steady state condition two rules should be fulfilled over a complete commutation cycle of the converter 150 :
1. The flying capacitor network charge and discharge is equal (capacitor charge and voltage is the same at the beginning and the end of a cycle), i.e. 0=∫(I C ×dt). 2. The current through the inductor L is the same at the beginning and the end of the cycle, i.e. 0=∫(dI L ×dt).

The first condition may be achieved by setting the duration of the first and second phases. The second condition may be achieved using a third phase. In particular, the second condition may be achieved by operating the power converter 150 in a first or a second variant of a third phase. The first variant of the third phase is shown in FIG. 3 c and the second variant of the third phase is shown in FIG. 3 d.
The third phase ramps the current through the inductor without affecting the charge of the flying capacitors C 1 , C 2 . The duration of the third phase may be regulated by the target or reference output voltage V ref (e.g. V in /2) and for constant output current triggers the same inductor current I L at the beginning of each cycle (consisting of the first, second and third phase). In case V in >2×V out the configuration from FIG. 3 d is typically selected (i.e. the first variant), otherwise the configuration from FIG. 3 c is selected (i.e. the second variant).
The third phase may be implemented only following the second phase or, for reduced inductor current ripple, may also be inserted between the first phase and the second phase. The inductor current ripple increases with V out being different from its optimum value of ½×V in . This ripple may be compensated via an increased switching frequency, but in both cases the conversion efficiency is reduced.
The converter 150 may be operated in an optional fourth phase (shown in FIG. 3 e ), where current through the inductor is zero and I out is provided by the output capacitor C out alone. This phase may be used in case the commutation cycle provides more average current than is pulled from the output. During the fourth phase all switches may be open (at least switches S 1 , S 4 , S 5 and S 8 ). The fourth phase may be inserted when the inductor current I L is crossing zero. The fourth phase may be referred to as a Discontinuous Conduction Mode (DCM), Pulse Frequency Modulation Mode (PFM) or Pulse Skipping Mode. The fourth phase regulates the output voltage/output current down by temporally stopping current through the inductor. The fourth phase may be terminated when V out (or I out ) has dropped below a minimum threshold (hysteretic control).
If a ground shift of the negative potential of the input voltage V in related to the negative potential of the output voltage V out is not relevant in a specific application, the circuitry 400 of FIG. 4 a may be a useful variant. It implements the input ripple cancellation with a reduced number of switches compared to the power converter 150 . The power converter 400 may be operated in at least three phases as outlined in the context of FIGS. 3 a through 3 e . A typical input for such a converter cell 400 is the rectifier output of an AC/DC transformer or a wireless charging coil as shown in the circuitry 410 of FIG. 4 b.
Another variant of the invented circuitry 150 of FIG. 1 b is shown in FIG. 4 c . A typical application for the circuitry 420 of FIG. 4 c is e.g. the core supply of low voltage/high performance application processors from a multi-cell (e.g. 2-cell) battery pack (with e.g. Vbat≧6V, Vout≦1.5V). The power converter 420 may be operated in at least three phases as outlined in the context of FIGS. 3 a through 3 e . The phases, notably the first and the second phase, may be partitioned into different fractions during which the respective inductors are coupled in series with the capacitor. In other words, the inductors may be operated in an interleaved manner. Furthermore, the inductors may be used concurrently (e.g. during a further fraction of the first and/of the second phases).
The architecture 420 of FIG. 4 c reduces the number of switching capacitors, but uses multiple smaller inductors, each sized for a fraction of the maximum output current of the converter 420 . The switches S 5 and S 8 to Ground enable the independent switching and/or regulation of the first and second inductors L 1 , L 2 (including interleaved switching for ripple cancellation) and improve the conversion efficiency, notably at low output voltage. The switches S 5 and S 7 are arranged in a parallel connection with the switching capacitor of the converter 420 . Conduction loss may be relatively low for the converter 420 , because the converter 420 comprises a reduced number of switches, notably between the inductor input and the supply rails V in and Ground, compared to other architectures.
An improved input ripple cancellation may be achieved when running two cells 420 from FIG. 4 c in an interleaved e.g. four inductors configuration 430 as shown in FIG. 4 d.
An alternative example of circuit 110 with optimized efficiency for a conversion ratio D˜0.25 and below is shown as circuit 440 in FIG. 4 e . The circuit 440 comprises a second level divider stage 441 . The circuit 400 cascades a capacitive voltage divider-stage 441 with a multi-level buck converter 100 . In a typical example, the switches S 5 & S 7 toggle their state in parallel with switches S 6 & S 8 , synchronized with the switching of the multi-level buck converter at a rate that is half or 1/k of its cycle frequency. Thus the current is pulled from the input only every 2 nd (or every k) cycle of the cascaded power converter 440 .
The input current ripple caused by converter periods not pulling current from the input can be reduced with another example converter 450 connecting two interleaved instances of the 2 nd level divider-stage 441 as shown in FIG. 4 f . The converter 450 comprises two interleaved 2 nd level divider-stages 441 which are cascaded with a three level buck converter 110 , 451 . The capacitors C 2 and C 3 in FIG. 4 f are implementing a voltage divider, each delivering ˜50% of the 3-level buck converter input current (with 50% being continuously pulled from V in ).
For further reduction of input current/input voltage ripple, the above shown 3-level buck converter 451 can be replaced with power converters as shown e.g. in FIGS. 1 a , 1 b , 4 a , 4 b , 4 c , and 4 d . For improved efficiency at very low conversion ratios (e.g. D≦0.125) the 3-level buck converter 451 may also be replaced with circuits as shown in FIGS. 4 e and 4 f.
The capacitive cell(s) shown in previous examples of FIGS. 1 a , 1 b , 4 a through 4 f may be replaced with other topologies like serial-parallel, Dickson, etc. topologies, thereby enabling optimum conversion efficiency also at divider ratios of e.g. 3:1, 1.5:1 (notably different to 2 n :1). As an example, the circuit 500 of FIG. 5 replaces the switching capacitors C 1 and C 2 from FIG. 1 a with two 3:1 cells of a Dickson topology.
The power converters described in the present document may make use of relatively low frequency switching for achieving high-efficient battery charging (wired and wireless) from input voltages which are substantially higher than the output voltage used for charging a battery pack. The input voltage ripple of the power converters may be improved using only a single small inductance at low switching frequency. The power converters may be implemented in a printed circuit board (PCB). As such, a low frequency multi-level buck converter in combination with small and low inductance coils are described for battery charging. Furthermore, low input current/input voltage ripple may be achieved from a low frequency switching multi-level buck converter in combination with a small single inductor and low input capacitance.
Using multi-level switching cells for the buck conversion of battery charging from input voltages that are substantially higher than the battery pack voltage enables low switching frequency in combination with low inductance (small size coils). The low switching frequency increases conversion efficiency (reduces dissipation power). The described architecture is adding ripple cancellation to multi-level buck converter cells without the requirement for multiple inductors. Furthermore, automatic charge regulation over the switching capacitance may be achieved, thereby removing the need for a regulation control loop.
FIG. 6 shows a flow chart of an example method 600 for controlling a power converter 150 . The power converter is configured to derive electrical power at an output voltage V out from electrical power at an input voltage V in wherein the power converter 150 comprises an inductor L a capacitor cell C 1 , C 2 and a plurality of switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8 .
The method 600 comprises controlling 601 the plurality of switches such that a commutation cycle of the power converter 150 comprises a first phase, during which the capacitor cell and the inductor are arranged in series and during which a voltage across the serial arrangement of the capacitor cell and the inductor corresponds to V in −V out . Furthermore, the method 600 comprises controlling 602 the plurality of switches such that the commutation cycle of the power converter comprises a second phase, during which the capacitor cell and the inductor are arranged in series and during which the voltage across the serial arrangement of the capacitor cell and the inductor corresponds to −V out . In addition, the method 600 comprises controlling 603 the plurality of switches such that the commutation cycle of the power converter comprises a third phase, during which the capacitor cell is floating and during which the voltage across the inductor corresponds to V in −V out or to −V out . By controlling the power converter according to method 600 , the ripple of the input voltage/input current may be reduced. Furthermore, the use of a capacitor cell in conjunction with an inductor enables the use of inductors of reduced inductance, thereby providing power converters of reduced size. In addition, the power dissipation of the power converter may be reduced.
It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiment outlined in the present document are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.