(en)A system may comprise a symbol mapper circuit that outputs C′ quadrature amplitude modulation (QAM) symbols per orthogonal frequency division multiplexing (OFDM) symbol. The system may also comprise circuitry operable to process said C′ QAM symbols using a circulant matrix to generate a particular OFDM symbol consisting of C+Δ subcarriers, where C′ is a first integer, C is a second integer less than C′, and Δ is an integer equal to the number of non-data-carrying subcarriers in the particular OFDM symbol. The circulant matrix may be a P×P matrix, where P is an integer less than C′. The system may comprise a nonlinear circuit that introduces nonlinear distortion to said particular OFDM symbol.

1.ApplicationNumber: US-201414329100-A
1.PublishNumber: US-2015010108-A1
2.Date Publish: 20150108
3.Inventor: ELIAZ AMIR
REUVEN ILAN

4.Inventor Harmonized: ELIAZ AMIR(IL)
REUVEN ILAN(IL)

5.Country: US
6.Claims:
(en)A system may comprise a symbol mapper circuit that outputs C′ quadrature amplitude modulation (QAM) symbols per orthogonal frequency division multiplexing (OFDM) symbol. The system may also comprise circuitry operable to process said C′ QAM symbols using a circulant matrix to generate a particular OFDM symbol consisting of C+Δ subcarriers, where C′ is a first integer, C is a second integer less than C′, and Δ is an integer equal to the number of non-data-carrying subcarriers in the particular OFDM symbol. The circulant matrix may be a P×P matrix, where P is an integer less than C′. The system may comprise a nonlinear circuit that introduces nonlinear distortion to said particular OFDM symbol.

7.Description:
(en)CLAIM OF PRIORITY
This patent application is a continuation of Ser. No. 13/921,665 now issued as U.S. Pat. No. 8,781,008, which in turn claims priority to U.S. Provisional Patent Application Ser. No. 61/662,085 titled “Apparatus and Method for Efficient Utilization of Bandwidth” and filed on Jun. 20, 2012, now expired, U.S. Provisional Patent Application Ser. No. 61/726,099 titled “Modulation Scheme Based on Partial Response” and filed on Nov. 14, 2012, now expired, U.S. Provisional Patent Application Ser. No. 61/729,774 titled “Modulation Scheme Based on Partial Response” and filed on Nov. 26, 2012, now expired, U.S. Provisional Patent Application Ser. No. 61/747,132 titled “Modulation Scheme Based on Partial Response” and filed on Dec. 28, 2012, now expired, U.S. Provisional Patent Application Ser. No. 61/768,532 titled “High Spectral Efficiency over Non-Linear, AWGN Channels” and filed on Feb. 24, 2013, now expired, and U.S. Provisional Patent Application Ser. No. 61/807,813 titled “High Spectral Efficiency over Non-Linear, AWGN Channels” and filed on Apr. 3, 2013, now expired, and which is a continuation-in-part of U.S. patent application Ser. No. 13/755,008 titled “Dynamic Filter Adjustment for Highly-Spectrally-Efficient Communications” and filed on Jan. 31, 2013.
Each of the above applications is hereby incorporated herein by reference in its entirety.


INCORPORATIONS BY REFERENCE
This patent application makes reference to:
U.S. patent application Ser. No. 13/754,964 (attorney docket no. 26150U502), titled “Low-Complexity, Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,582,637; U.S. patent application Ser. No. 13/754,998 (attorney docket no. 26151U502), titled “Design and Optimization of Partial Response Pulse Shape Filter,” and filed on Jan. 31, 2013; U.S. patent application Ser. No. 13/755,001 (attorney docket no. 26152U502), titled “Constellation Map Optimization for Highly Spectrally Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,675,769; U.S. patent application Ser. No. 13/755,008 (attorney docket no. 26153U502), titled “Dynamic Filter Adjustment for Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,571,131; U.S. patent application Ser. No. 13/755,011 (attorney docket no. 26156U502), titled “Timing Synchronization for Reception of Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,559,494; U.S. patent application Ser. No. 13/755,014 (attorney docket no. 26157U502), titled “Signal Reception Using Non-Linearity-Compensated, Partial Response Feedback,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,559,496; U.S. patent application Ser. No. 13/755,018 (attorney docket no. 26158U502), titled “Feed Forward Equalization for Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,599,914; U.S. patent application Ser. No. 13/755,021 (attorney docket no. 26159U502), titled “Decision Feedback Equalizer for Highly Spectrally Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,665,941; U.S. patent application Ser. No. 13/755,025 (attorney docket no. 26160U502), titled “Decision Feedback Equalizer with Multiple Cores for Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013; U.S. patent application Ser. No. 13/755,026 (attorney docket no. 26161U502), titled “Decision Feedback Equalizer Utilizing Symbol Error Rate Biased Adaptation Function for Highly Spectrally Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,559,498; U.S. patent application Ser. No. 13/755,028 (attorney docket no. 26163U502), titled “Coarse Phase Estimation For Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,548,097; U.S. patent application Ser. No. 13/755,039 (attorney docket no. 26164U502), titled “Fine Phase Estimation for Highly Spectrally Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,565,363; U.S. patent application Ser. No. 13/755,972 (attorney docket no. 26165U502), titled “Multi-Mode Transmitter for Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,744,003; U.S. patent application Ser. No. 13/755,043 (attorney docket no. 26166U502), titled “Joint Sequence Estimation of Symbol and Phase With High Tolerance Of Nonlinearity,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,605,832; U.S. patent application Ser. No. 13/755,050 (attorney docket no. 26168U502), titled “Adaptive Non-Linear Model for Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,553,821; U.S. patent application Ser. No. 13/755,052 (attorney docket no. 26169U502), titled “Pilot Symbol-Aided Sequence Estimation for Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013; U.S. patent application Ser. No. 13/755,054 (attorney docket no. 26171U502), titled “Method and System for Corrupt Symbol Handling for Providing High Reliability Sequences,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,571,146; U.S. patent application Ser. No. 13/755,060 (attorney docket no. 26172U502), titled “Method and System for Forward Error Correction Decoding with Parity Check for Use in Low Complexity Highly-spectrally-efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,566,687; U.S. patent application Ser. No. 13/755,061 (attorney docket no. 26174U502), titled “Method and System for Quality of Service (QoS) Awareness in a Single Channel Communication System,” and filed on Jan. 31, 2013; U.S. patent application Ser. No. 13/756,079 (attorney docket no. 26467U502), titled “Pilot Symbol Generation for Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,665,992; U.S. patent application Ser. No. 13/755,065 (attorney docket no. 26468U502), titled “Timing Pilot Generation for Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,548,072; U.S. patent application Ser. No. 13/756,010 (attorney docket no. 26469U502), titled “Multi-Mode Receiver for Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013; U.S. patent application Ser. No. 13/755,068 (attorney docket no. 26470U502), titled “Forward Error Correction with Parity Check Encoding for use in Low Complexity Highly-spectrally-efficient Communications,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,572,458; U.S. patent application Ser. No. 13/756,469 (attorney docket no. 26480U502), titled “Highly-Spectrally-Efficient Receiver,” and filed on Jan. 31, 2013, now patented as U.S. Pat. No. 8,526,523; U.S. patent application Ser. No. 13/921,665 (attorney docket no. 26650U502), titled “Highly-Spectrally-Efficient Reception Using Orthogonal Frequency Division Multiplexing,” and filed on Jun. 19, 2013; U.S. patent application Ser. No. 13/921,749 (attorney docket no. 26651U502), titled “Multi-Mode Orthogonal Frequency Division Multiplexing Transmitter for Highly-Spectrally-Efficient Communications,” and filed on Jun. 19, 2013; and U.S. patent application Ser. No. 13/921,813 (attorney docket no. 26652U502), titled “Multi-Mode Orthogonal Frequency Division Multiplexing Receiver for Highly-Spectrally-Efficient Communications,” and filed on Jun. 19, 2013 now patented as U.S. Pat. No. 8,681,889.

Each of the above applications is hereby incorporated herein by reference in its entirety.
TECHNICAL FIELD
Aspects of the present application relate to electronic communications.
BACKGROUND
Existing communications methods and systems are overly power hungry and/or spectrally inefficient. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such approaches with some aspects of the present method and system set forth in the remainder of this disclosure with reference to the drawings.
BRIEF SUMMARY
Methods and systems are provided for highly-spectrally-efficient communications using orthogonal frequency division multiplexing, substantially as illustrated by and/or described in connection with at least one of the figures, as set forth more completely in the claims.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a diagram of an example OFDM transmitter.
FIG. 1B depicts simulation results of an example cyclic filter for a highly-spectrally-efficient OFDM transmitter.
FIG. 1C depicts a flowchart describing operation of an example implementation of a highly-spectrally-efficient OFDM transmitter.
FIG. 2A is a diagram of an example OFDM receiver.
FIGS. 2B and 2C depict a flowchart describing operation of an example implementation of a highly-spectrally-efficient OFDM receiver.
FIG. 2D depicts a flowchart describing operation of an example decoding circuit of a highly-spectrally-efficient OFDM receiver.
FIG. 3 is a flowchart describing a process for mitigating the effects of frequency-selective fading in highly-spectrally-efficient OFDM communication system.



DETAILED DESCRIPTION
As utilized herein the terms “circuits” and “circuitry” refer to physical electronic components (i.e. hardware) and any software and/or firmware (“code”) which may configure the hardware, be executed by the hardware, and or otherwise be associated with the hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing a first one or more lines of code and may comprise a second “circuit” when executing a second one or more lines of code. As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. As utilized herein, the term “exemplary” means serving as a non-limiting example, instance, or illustration. As utilized herein, the terms “e.g.,” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations. As utilized herein, circuitry is “operable” to perform a function whenever the circuitry comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled, or not enabled, by some user-configurable setting.
Orthogonal Frequency Division Multiplexing (OFDM) has gained traction in recent years in high-capacity wireless and wireline communication systems such as WiFi (IEEE Std 802.11n/ac), 3GPP-LTE, and G.hn. One advantage of OFDM is that it can reduce the need for complicated equalization over frequency selective channels. It is particularly powerful in combination with multiple independent spatial streams and multiple antennas, Multiple Input Multiple Output (MIMO) systems. One advantage of OFDM is that it can reduce or eliminate the need for complicated equalization over frequency selective channels. Conventional MIMO-OFDM solutions are based on suboptimal Zero Forcing, SIC (Successive Interference Cancellation), and minimum mean square error (MMSE) receivers. These detection algorithms are significantly inferior to maximum likelihood (ML) and near-ML receivers. Lately, in emerging standards, constellation size continues to increase (256-QAM, 1024-QAM, and so on). The associated ML state space of such solutions is N SS , where N and SS stand for the constellation size and total number of MIMO spatial streams, respectively. Consequently, aspects of this disclosure pertain to reduced state/complexity ML decoders that achieve high performance.
Example implementations of the present disclosure may use relatively small constellations with partial response signaling that occupies around half the bandwidth of “ISI-free” or “full response” signaling. Thus, the ML state space is reduced significantly and cost effectiveness of reduced complexity ML detection is correspondingly improved. Additionally, aspects of this disclosure support detection in the presence of phase noise and non-linear distortion without the need of pilot symbols that reduce capacity and spectral efficiency. The spectral compression also provides multidimensional signal representation that improves performance in an AWGN environment as compared to conventional two-dimensional QAM systems. In accordance with an implementation of this disclosure, transmitter shaping filtering may be applied in the frequency domain in order to preserve the independency of the OFDM symbols.
FIG. 1A is a diagram of an example OFDM transmitter. The example transmitter 100 comprises a symbol mapper circuit 102 , an inter-symbol correlation (ISC) generation circuit 104 , a decimation circuit 108 , a serial-to-parallel circuit 108 , an inverse fast Fourier transform (IFFT) circuit 112 , a parallel-to-serial circuit 114 , a cyclic prefix and windowing circuit 116 , and a transmit front-end circuit 118 . In the example implementation shown, the transmitter transmits into a channel 120 .
The symbol mapper circuit 102 , may be operable to map, according to a selected modulation scheme, bits of a bitstream to be transmitted (“Tx_bitstream”) to symbols. For example, for a quadrature amplitude modulation (QAM) scheme having a symbol alphabet of N (N-QAM), the mapper may map each Log 2 (N) bits of the Tx_bitstream to a single symbol represented as a complex number and/or as in-phase (I) and quadrature-phase (Q) components. Although N-QAM is used for illustration in this disclosure, aspects of this disclosure are applicable to any modulation scheme (e.g., pulse amplitude modulation (PAM), amplitude shift keying (ASK), phase shift keying (PSK), frequency shift keying (FSK), etc.). Additionally, points of the N-QAM constellation may be regularly spaced (“on-grid”) or irregularly spaced (“off-grid”). Furthermore, the symbol constellation used by the mapper 102 may be optimized for best bit-error rate (BER) performance (or adjusted to achieve a target BER) that is related to log-likelihood ratio (LLR) and to optimizing mean mutual information bit (MMIB) (or achieving a target MMIB). The Tx_bitstream may, for example, be the result of bits of data passing through a forward error correction (FEC) encoder and/or an interleaver. Additionally, or alternatively, the symbols out of the mapper 102 may pass through an interleaver.
The ISC generation circuit 104 may be operable to filter the symbols output by the mapper 102 to generate C′ virtual subcarrier values (the terminology “virtual subcarrier” is explained below) having a significant, controlled amount inter-symbol correlation among symbols to be output on different subcarriers (i.e., any particular one of the C′ virtual subcarrier values may be correlated with a plurality of the C′ symbols output by mapper 102 ). In other words, the inter-symbol correlation introduced by the ISC generation circuit may be correlation between symbols to be output on different subcarriers. In an example implementation, the ISC generation circuit 104 may be a cyclic filter.
The response of the ISC generation circuit 104 may be determined by a plurality of coefficients, denoted p (where underlining indicates a vector), which may be, for example, stored in memory 124 . In an example implementation, the ISC generation circuit 104 may perform a cyclic (or, equivalently, “circular”) convolution on sets of C′ symbols from the mapper 102 to generate sets of C′ virtual subcarrier values conveyed as signal 105 . In such an implementation, the ISC generation circuit 104 may thus be described as a circulant matrix that multiplies an input vector of C′ symbols by a C′×C′ matrix, where each row i+1 of the matrix may be a circularly shifted version of row i of the matrix, i being an integer from 1 to C′. For example, for C′=4 (an arbitrary value chosen for illustration only) and p =[p1 p2 p3 p4], the matrix may be as follows:






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In another example, the length of p may be less than C′, and zero padding may be used to fill the rows and/or columns to length C′ and/or pad the rows and/or columns. For example, C′ may be equal to 6 and the matrix above (with p having four elements) may be padded to create a six element vector p Z =[p1 p2 p3 p4 0 0] and then p Z may be used to generate a 6 by 6 matrix in the same way that p was used to generate the 4 by 4 matrix. As another example, only the rows may be padded such that the result is a C′×LP matrix, where LP is the length of p (e.g., a 4×6 matrix in the above example). As another example, only the columns may be padded such that the result is a LP×C′ matrix, where LP is the length of p (e.g., a 6×4 matrix in the above example).
The decimation circuit 108 may be operable to decimate groups of C′ virtual subcarrier values down to C transmitted physical subcarrier values (the term “physical subcarrier” is explained below). Accordingly, the decimation circuit 108 may be operable to perform downsampling and/or upsampling. The decimation factor may be an integer or a fraction. The output of the decimator 108 hence comprises C physical subcarrier values per OFDM symbol. The decimation may introduce significant aliasing in case that the ISC generation circuit 104 does not confine the spectrum below the Nyquist frequency of the decimation. However, in example implementations of this disclosure, such aliasing is allowed and actually improves performance because it provides an additional degree of freedom. The C physical subcarrier values may be communicated using C of C+Δ total subcarriers of the channel 120 . Δ may correspond to the number of OFDM subcarriers on the channel 120 that are not used for transmitting data. For example, data may not be transmitted a center subcarrier in order to reduce DC offset issues. As another example, one or more subcarriers may be used as pilots to support phase and frequency error corrections at the receiver. Additionally, zero subcarrier padding may be used to increase the sampling rate that separates the sampling replicas and allow the use of low complexity analog circuitry. The C+Δ subcarriers of channel 120 may be spaced at approximately (e.g., within circuit tolerances) BW/(C+Δ) (according to the Nyquist criterion) and with effective OFDM symbol duration of less than or equal to (C+Δ)/BW (according to the Nyquist criterion). Aspects of the invention may, however, enable the receiver to recover the original C′ symbols from the received OFDM symbol (Thus the reason for referring to C′ as the number of “virtual subcarriers”). This delivery of C′ symbols using C effective subcarriers of bandwidth BW/(C+Δ), and OFDM symbol timing of less than or equal to (C+Δ)/BW thus corresponds to a bandwidth reduction of (C′+Δ)/(C+Δ) or, equivalently, a symbol rate increase of C′/C over conventional OFDM systems (assuming the same number, A, of unused subcarriers in the conventional system).
To reduce complexity, in an example implementation, the functionalities of 104 and 108 may be merged by calculating only a subset (C S ) of the C physical subcarriers subset from C′ by taking out the rows of the matrix that are related to the decimated virtual subcarriers of the ISC generating, C′×C′ matrix. For example, decimation of factor of 2 may be achieved by eliminating the even column vectors of the C′×C′ matrix described in paragraph [0021] (assuming, for purposes of this example, that the information symbol vector (length of C′) is a row vector that left multiplies the matrix).
Generally speaking, in an example implementation wherein the circuit 104 is a cyclic filter, methods and systems of designing the ISC generation circuit 104 may be similar to methods and systems described in U.S. patent application Ser. No. 13/754,998 titled “Design and Optimization of Partial Response Pulse Shape Filter,” which is incorporated by reference above. Similar to the design of the filter(s) in the single-carrier case described in U.S. patent application Ser. No. 13/754,998, the design of a cyclic filter implementation of the circuit 104 may be based on using the symbol error rate (SER) union bound as a cost function and may aim to maximize the Euclidean distance associated with one or more identified error patterns. Using a shaping filter characterized by the coefficients p , the distance induced by error pattern ε may be expressed as:
δ 2 ( ε , p )=Σ n |Σ k p [n−k] ε [k] | 2 =Σ k Σ l ε [k] ε [l] *Σ n p [n−k] p [n−l] * Eq. 1A

Assuming, for purposes of illustration, a spectral compression factor 2, then, after decimation by 2, EQ. 1A becomes:
δ 2 2 ( ε , p )=Σ n |Σ k p [2n−k] ε [k] | 2 =Σ n Σ k ε [2n−2k] p [2k] Σ k ε [2n−2k+1] p [2k−1] | 2 Eq. 1B

Where the right-hand-side summation relates to odd-indexed symbols and the left-hand-side summation relates to even-indexed symbols. Eq. 1B may then be rewritten as:









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In Eq. 1C, the first and second summation terms are associated with the distance of the even-indexed and odd-indexed virtual subcarriers respectively. Accordingly, one goal in designing a cyclic filter implementation of ISC generation circuit 104 may be to maximize the first and second terms of Eq. 1C. The third term takes on both positive and negative values depending on the error pattern. In general, this term will reduce the minimum distance related to the most-probable error patterns. Accordingly, one goal in designing a cyclic filter implementation of ISC generation circuit 104 may be to minimize the third term of Eq. 1C (i.e., minimizing cross-correlation between even and odd virtual subcarriers). Additionally or alternatively, a cyclic filter implementation of ISC generation circuit 104 may be designed such that the first and second terms should have similar levels, which may correspond to even-indexed and odd-indexed symbol sequences have comparable distances (i.e., seeking energy balance between even-indexed and odd-indexed virtual subcarriers).
In presence of frequency-selective fading channel, the inter-subcarrier correlation created by 104 (by filtering or by matrix multiplication, for example) may be used to overcome the frequency-selective fading and to improve detection performance at the receiver. The processing of inter-subcarrier correlation may be perceived as “analog interleaving” over the frequency domain that spreads each of the C′ information symbols over a plurality of frequency subcarriers. As a result of this “analog interleaving,” a notch in one of the subcarriers will have a relatively low impact on detection, assuming that rest of subcarriers that are carrying that information symbol are received with sufficiently-high SNR.
In case of frequency selective fading channel, feedback from the receiving device may be used to dynamically adapt transmission properties. An example process for such dynamic adaption is shown in FIG. 3 .
In block 302 frequency selective fading is causing a significant notch that is critically impacting one or more subcarriers. For example, the notch may be reducing the received SNR of the subcarrier(s) below a certain level (e.g., a level that is predetermined and/or algorithmically controlled during run time).
In block 304 , an identification of such impacted subcarrier(s) may be sent from the receiving device to the transmitting device (e.g., over a control channel).
In block 306 , in response to receiving the indication sent in block 304 , the transmitting device disables transmission of data over the impacted subcarrier(s). The transmitting device may disable transmission of data over the impacted subcarrier(s) by, for example, reconfiguring the mapper 102 (e.g., changing the value of C′ and/or configuring the mapper 102 to insert pilot symbols between data symbols), changing p, reconfiguring the decimation circuit 108 (e.g., changing the value of C), and/or reconfiguring the mapping performed by the serial-to-parallel circuit 110 .
In block 308 , the receiving device may determine that data transmission on the disabled subcarriers should resume.
In block 310 , the instruction to resume data transmission on the disabled subcarrier(s) may be sent (e.g., via a control channel). In an example implementation, such a determination may be made by monitoring pilot signal(s) that the transmitting device transmits on the disabled subcarrier(s). For example, the receiving device may monitor a characteristic (e.g., SNR) of the pilot signal(s) and determine to resume use of the subcarriers(s) upon a significant and/or sustained change in the characteristic (e.g., upon SNR of the pilot signal(s) increasing above a determined threshold for a determined amount of time. In an example implementation, the determination to resume data transmission on the disabled subcarrier(s) may be based on the one or more characteristics of subcarriers adjacent to the disabled subcarrier(s). For example, while subcarrier N is disabled, the receiving device may monitor SNR of adjacent subcarriers N−1 and/or N+1, and may decide enable subcarrier N in response to a significant and/or sustained increase in the SNR of subcarrier(s) N−1 and/or N+1. The first example above for SNR estimation of disabled subcarrier(s) which is based on pilots, may be more accurate than the second example which is based on SNR estimation using adjacent subcarriers. However, the second example does not “waste” power on pilot subcarrier(s) transmission thus may provide higher power for the information (modulated) subcarriers assuming that the transmitted power is fixed. The relative increased power of the modulated subcarriers may improve decoding performance (e.g., SER, BER, packet error rate).
Similarly, feedback from the receiving device (e.g., in the form of subcarrier SNR measurements) may be used to adapt the ISC generation circuit 104 and/or decimation circuit 108 . Such adaptation may, for example, give relatively-high-SNR subcarriers relatively-high coefficients and relatively-low-SNR subcarriers relatively-low coefficients. Such adaptation of coefficients may be used to optimize communication capacity (or to achieve a target communication capacity) between the transmitting device and the receiving device. The control channel latency and adaptation rate may be controlled to be fast enough to accommodate channel coherence time.
Returning to FIG. 1B , additional, or alternative, design goals for the circuit 104 may stem from a desire to reduce complexity of the sequence estimation in the receiver. As an example, one design goal may be, as described in U.S. patent application Ser. No. 13/754,998, maximizing the magnitude of coefficients of “early” (or low-indexed) taps of a cyclic filter implementation of circuit 104 . As another example, one design goal may be, as described in U.S. patent application Ser. No. 13/754,998, minimizing the cumulative power of the “late” (or high-indexed) taps of a cyclic filter implementation of circuit 104 .
As shown by the example simulation results in FIG. 1B (compression factor=2 used for purposes of illustration), a complex-valued shaping filter can exploit the full spectrum and make the even-indexed (“ph 1”) and odd-indexed responses (“ph 2”) substantially orthogonal by using disjoint parts of the spectrum. FIG. 1B shows an example of the frequency response of the even-indexed and odd-indexed coefficients of a cyclic filter implementation of circuit 104 that was designed in accordance with this disclosure. Also, shown in the lower portion of FIG. 1B is the total/combined even and odd response, which, as can be seen, is substantially flat.
Returning to FIG. 1A , the serial-to-parallel circuit 110 may be operable to convert C physical subcarrier values conveyed serially as signal 109 to C physical subcarrier values input conveyed in parallels as signals 111 .
In an example implementation, the subcarrier values output by the decimation circuit 108 may be interleaved prior to being input to the circuit 112 and/or the circuit 110 may perform interleaving of the inputted subcarrier values. This interleaver may be operable to improve the tolerance to frequency selective fading caused by multipath that may impose wide notch that spans over several subcarriers. In this case the interleaver may be used to “spread” the notch over non-consecutive (interleaved) subcarriers and therefore reduce the impact of the notch on decoding performance.
Each of the signals 103 , 105 , 109 , and 111 may be frequency-domain signals. The inverse fast Fourier transform (IFFT) circuit 112 may be operable to convert the frequency-domain samples of signals 111 to time-domain samples of signals 113 .
The parallel-to-serial circuit 114 may be operable to convert the parallel signals 113 to a serial signal 115 .
The circuit 116 may be operable to process the signal 115 to generate the signal 117 . The processing may include, for example, insertion of a cyclic prefix. Additionally, or alternatively, the processing may include application of a windowing function to compensate for artifacts that may result when a receiver of the transmitted signal uses the FFT to recover information carried in the transmitted signal. Windowing applied the in transmitter 100 may be instead of, or in addition to, windowing applied in a receiver.
The transmitter front-end 118 may be operable to convert the signal 117 to an analog representation, upconvert the resulting analog signal, and amplify the upconverted signal to generate the signal 119 that is transmitted into the channel 120 . Thus, the transmitter front-end 118 may comprise, for example, a digital-to-analog converter (DAC), mixer, and/or power amplifier. The front-end 118 may introduce non-linear distortion and/or phase noise (and/or other non-idealities) to the signal 117 . The non-linearity of the circuit 118 may be represented as NL TX which may be, for example, a polynomial, or an exponential (e.g., Rapp model). The non-linearity may incorporate memory (e.g., Voltera series). In an example implementation, the transmitter 100 may be operable to transmit its settings that relate to the nonlinear distortion inflicted on transmitted signals by the front-end 118 . Such transmitted information may enable a receiver to select an appropriate nonlinear distortion model and associated parameters to apply (as described below).
The channel 120 may comprise a wired, wireless, and/or optical communication medium. The signal 119 may propagate through the channel 120 and arrive at a receiver such as the receiver described below with respect to FIG. 2A .
In various example embodiments, subcarrier-dependent bit-loading and time-varying bit-loading may also be used.
FIG. 1C depicts a flowchart describing operation of an example implementation of a highly-spectrally-efficient OFDM transmitter. The process begins with block 152 in which a baseband bitstream is generated (e.g., by an application running on a smartphone, tablet computer, laptop computer, or other computing device).
In block 154 , the baseband bitstream is mapped according to a symbol constellation. In the example implementation depicted, C′ (an integer) sets of log 2(N) bits of the baseband bitstream are mapped to C′ N-QAM symbols.
In block 156 , the C′ symbols are cyclically convolved, using a filter designed as described above with reference to FIG. 1A , to generate C′ virtual subcarrier values having a significant, controlled amount of inter-symbol correlation among symbols to be output on different subcarriers.
In block 158 , the C′ virtual subcarrier values output by the ISC generation circuit 104 may be decimated down to C physical subcarrier values, each of which is to be transmitted over a respective one of the C+Δ OFDM subcarriers of the channel 120 . In an example implementation, the decimation may be by a factor of between approximately 1.25 and 3.
In block 160 , the C physical subcarrier values are input to the IFFT and a corresponding C+Δ time-domain values are output for transmission over C+Δ subcarriers of the channel 120 .
In block 162 , a cyclic prefix may be appended to the C time domain samples resulting from block 160 . A windowing function may also be applied to the samples after appending the cyclic prefix.
In block 164 the samples resulting from block 162 may be converted to analog, upconverted to RF, amplified, and transmitted into the channel 120 during a OFDM symbol period that is approximately (e.g., within circuit tolerances) (C+Δ)/BW.
FIG. 2A is a diagram of an example OFDM receiver. The example receiver 200 comprises a front-end 202 , a cyclic prefix and windowing circuit 204 , a serial-to-parallel conversion circuit 208 , a frequency correction circuit 206 , a fast Fourier transform (FFT) circuit 210 , a per-tone equalizer 212 , a phase correction circuit 214 , a parallel-to-serial conversion circuit 216 , a decoding circuit 218 , a controlled combined inter-symbol correlation (ISC) and/or inter-subcarrier interference (ICI) model (Controlled ISCI Model) circuit 220 , a carrier recovery loop circuit 222 , a FEC decoder circuit 232 , and a performance indicator measurement circuit 234 .
The receiver front-end 202 may be operable to amplify, downconvert, and/or digitize the signal 121 to generate the signal 203 . Thus, the receiver front-end 202 may comprise, for example, a low-noise amplifier, a mixer, and/or an analog-to-digital converter. The front-end 202 may, for example, sample the received signal 121 at least C+Δ times per OFDM symbol period. Due to non-idealities, the receiver front-end 202 may introduce non-linear distortion and/or phase noise to the signal 203 . The non-linearity of the front end 202 may be represented as NL Rx which may be, for example, a polynomial, or an exponential (e.g., Rapp model). The non-linearity may incorporate memory (e.g., Voltera series).
The circuit 204 may be operable to process the signal 203 to generate the signal 205 . The processing may include, for example, removal of a cyclic prefix. Additionally, or alternatively, the processing may include application of a windowing function to compensate for artifacts that may result from use of an FFT on a signal that is not periodic over the FFT window. Windowing applied in the transmitter 100 may be instead of, or in addition to, windowing applied in a receiver. The output of the circuit 204 may comprise C samples of the received signal corresponding to a particular OFDM symbol received across C+Δ subcarriers.
The frequency correction circuit 206 may be operable to adjust a frequency of signal 205 to compensate for frequency errors which may result from, for example, limited accuracy of frequency sources used for up and down conversions. The frequency correction may be based on feedback signal 223 from the carrier recovery circuit 222 .
The serial-to-parallel conversion circuit 208 may be operable to convert C time-domain samples output serially as the signal 207 to C time-domain samples output in parallel as signals 209 .
In an example implementation, where interleaving of the subcarrier values was performed in transmitter, the phase/frequency-corrected, equalized subcarrier values output at link 215 may be de-interleaved prior to being input to the circuit 218 and/or the circuit 216 may perform de-interleaving of the subcarrier values. In this case the Controlled ISCI Model 220 (comprising the combined ISC model used by the modulator and/or ICI model reflecting the channel non-idealities) should consider the interleaving operation.
Each of the signals 203 , 205 , 207 , and 209 may be time-domain signals. The fast Fourier transform (FFT) circuit 210 may be operable to convert the time-domain samples conveyed as signals 209 to C physical subcarrier values conveyed as signals 211 .
The per-tone equalizer 212 may be operable to perform frequency-domain equalization of each of the C physical subcarrier values to compensate for non-idealities (e.g., multipath, additive white Gaussian noise, (AWGN), etc.) experienced by a corresponding one of the C OFDM subcarriers. In an example implementation, the equalization may comprise multiplying a sample of each of signals 211 by a respective one of C complex coefficients determined by the equalization circuit 212 . Such coefficients may be adapted from OFDM symbol to OFDM symbol. Adaption of such coefficients may be based on decisions of decoding circuit 218 . In an example implementation, the adaptation may be based on an error signal 221 defined as the difference, output by circuit 230 , between the equalized and phase-corrected samples of signal 217 and the corresponding reconstructed signal 227 b output by the decoding circuit 218 . Generation of the reconstructed signal 227 b may be similar to generation of the reconstructed signal 203 in the above-incorporated U.S. patent application Ser. No. 13/754,964 (but modified for the OFDM case, as opposed to the single-carrier case described therein) and/or as described below with reference to FIG. 2D .
The phase correction circuit 214 may be operable to adjust the phase of the received physical subcarrier values. The correction may be based on the feedback signal 225 from the carrier recovery circuit 222 and may compensate for phase errors introduced, for example, by frequency sources in the front-end of the transmitter and/or the front-end 202 of the receiver.
The parallel-to-serial conversion circuit 216 may convert the C physical subcarrier values output in parallel by circuit 214 to a serial representation. The physical subcarrier values bits may then be conveyed serially to the decoding circuit 218 . Alternatively, 216 may be bypassed (or not present) and the decoding at 218 may be done iteratively over the parallel (vector) signal 215 .
The controlled ISCI model circuit 220 may be operable to store tap coefficients p and/or nonlinearity model The stored values may, for example, have been sent to the receiver 200 by the transmitter 100 in one or more control messages. The controlled ISCI model circuit 220 may be operable to convert a time-domain representation of a nonlinearity model to a frequency domain representation. The model 220 may, for example, store (e.g., into a look-up table) multiple sets of filter coefficients and/or nonlinearity models and may be operable to dynamically select (e.g., during operation based on recent measurements) the most appropriate one(s) for the particular circumstances.
The decoding circuit 218 may be operable to process the signal 217 to recover symbols carried therein. In an example implementation, the decoding circuit 218 may be an iterative maximum likelihood or maximum a priori decoder that uses symbol slicing or other techniques that enable estimating individual symbols rather than sequences of symbols. In another example implementation, the decoding circuit 218 may be a sequence estimation circuit operable to perform sequence estimation to determine the C′ symbols that were generated in the transmitter corresponding to the received OFDM symbol. Such sequence estimation may be based on maximum likelihood (ML) and/or maximum a priori (MAP) sequence estimation algorithm(s), including reduced-complexity (e.g., storing reduced channel state information) versions thereof. The decoding circuit 218 may be able to recover the C′ symbols from the C physical subcarriers (where C′>C) as a result of the controlled inter-symbol correlation and/or aliasing that was introduced by the transmitter (e.g., as a result of the processing by the ISC generation circuit 104 and/or the aliasing introduced by the decimation circuit 108 ). The decoding circuit 218 may receive, from circuit 220 , a frequency-domain controlled ISCI model which may be based on non-linearity, phase noise, and/or other non-idealities experienced by one or more of the C physical subcarrier values arriving at the decoding circuit 218 .
The decoding circuit 218 may use the controlled ISCI model to calculate metrics similar to the manner in which a model is used to calculate metrics in above-incorporated U.S. patent application Ser. No. 13/754,964 (but modified for the OFDM case as opposed to the single-carrier case described therein) and/or as described below with reference to FIG. 2C . The decoding circuit 218 may also use the controlled ISCI model provided by circuit 220 to generate signals 227 a and 227 b , as described herein. In an example implementation, the decoding circuit 218 is operable to get at its input C equalized and phase-corrected physical subcarrier values and generate LLR values associated with the bits of the C′ constellation symbols that where originally loaded over the virtual subcarriers of the WAM-OFDM transmitter. The LLRs may be generated by checking multiple hypotheses of C′ constellation symbols based on the received samples. The best hypothesis may be used to generate the symbols and hard bits detection. In case of using a soft error correction code, an LLR interface that reflects the reliability of the bits (analog signal) rather than the hard bits (i.e., “0”, “1”) may be used. A remaining one or more of the hypotheses (the second-best, third-best, etc.) may be used to generate the LLR values. For example, assuming that a particular bit was detected as “1” according to the best hypothesis, the LLR for this bit may be provided from the distance of the best hypothesis to the second best hypothesis that estimates this particular bit as “0”. The LLR values for the different virtual subcarriers may be weighted according to their respective SNR. In case of frequency-selective fading channel, each subcarrier may have a different gain that corresponds to a different SNR per subcarrier. Because LLR value reflects the bit reliability, in an example implementation, the LLRs may be weighted according to the appropriate subcarrier gain to achieve Maximum Likelihood performance. In an example implementation, log-likelihood ratios (LLRs) determined in a receiver (e.g., in circuit 218 ) may have a noise variance component that varies with subcarrier. This may be because the per-subcarrier channel gain (due, for example, to the analog channel selection filter circuits and channel) may vary with frequency but the RF front-end gain at the receiver may be fixed.
For each received OFDM symbol, the circuit 220 may generate a frequency-domain controlled ISCI model of the channel over which the OFDM symbol was received. The controlled ISCI model of 220 may account for non-linear distortion experienced by the received OFDM symbol, phase noise experienced by the received OFDM symbol, and/or other non-idealities. For example, a third-order time domain distortion may be modeled in the frequency domain as:





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The carrier recovery loop circuit 222 may be operable to recover phase and frequency of one or more of the C OFDM subcarriers of the channel 120 . The carrier recovery loop 222 may generate a frequency error signal 223 and a phase error signal 225 . The phase and/or frequency error may be determined by comparing physical subcarrier values of signal 217 to a reconstructed signal 227 a . Accordingly, the frequency error and/or phase error may be updated from OFDM symbol to OFDM symbol. The reconstructed signal 227 b may be generated similar to the manner in which the reconstructed signal 207 of the above-incorporated U.S. patent application Ser. No. 13/754,964 (but modified for the OFDM case, as opposed to the single-carrier case described therein) and/or as described below with reference to FIG. 2D .
The performance indicator measurement circuit 234 may be operable to measure, estimate, and/or otherwise determine characteristics of received signals and convey such performance measurement indications to a transmitter collocated with the receiver 200 for transmitting the feedback to the remote side. Example performance indicators that the circuit 234 may determine and/or convey to a collocated transmitter for transmission of a feedback signal include: signal-to-noise ratio (SNR) per subcarrier (e.g., determined based on frequency-domain values at the output of FFT 210 and corresponding decisions at the output of the decoding circuit 218 and/or FEC decoder 232 ), symbol error rate (SER) (e.g., measured by decoding circuit 218 and conveyed to the circuit 234 ), and/or bit error rate (BER) (e.g., measured by the FEC decoder and conveyed to the circuit 234 ).
FIGS. 2B and 2C depict a flowchart describing operation of an example implementation of a highly-spectrally-efficient OFDM receiver. The process begins with block 242 in which an OFDM symbol arrives, as signal 121 , at front-end 202 and is amplified, down-converted, and digitized to generate C+Δ+P time-domain samples of the OFDM symbol, where P is the size of the cyclic prefix.
In block 244 , the cyclic prefix may be removed and a windowing function may be applied.
In block 246 , frequency correction may be applied to the time-domain samples based on an error signal 223 determined by the carrier recovery circuit 222 .
In block 248 , the frequency-corrected time-domain samples are converted to frequency-corrected frequency-domain physical subcarrier values by the FFT circuit 210 .
In block 250 , the frequency-corrected physical subcarrier values output by the FFT are equalized in the frequency domain by the per-subcarrier equalizer circuit 212 .
In block 252 , one or more of the frequency-corrected and equalized physical subcarrier values are phase corrected based on a phase correction signal 225 generated by the carrier recovery circuit 222 .
In block 254 , the vector of C frequency-corrected, equalized, and phase-corrected received physical subcarrier values is input to decoding circuit 218 and sequence estimation is used to determine the best estimates of the vector of C′ symbols that resulted in the vector of C frequency-corrected, equalized, and phase-corrected received physical subcarrier values. Example details of metric generation performed during the sequence estimation are described below with reference to FIG. 2C .
In block 256 , the best estimate of the vector of C′ symbols is determined by decoding circuit 218 and is output as signal 219 to FEC decoder 232 , which outputs corrected values on signal 233 . Example details of selecting the best candidate vector are described below with reference to FIG. 2C .
Referring to FIG. 2C , in block 262 , the decoding circuit 218 generates a plurality of candidate vectors (each candidate vector corresponding to a possible value of the vector of C′ symbols generated by the transmitter), and generates a corresponding plurality of reconstructed physical subcarrier vectors by applying the controlled ISCI model to the candidates.
In block 264 , the reconstructed physical subcarrier vectors are compared to the vector of frequency-corrected, equalized, and/or phase-corrected received physical subcarrier values to calculate metrics.
In block 266 , the candidate vector corresponding to the best metric is selected as the best candidate, and the C′ symbols of the best candidate are output as signal 219 , to, for example, FEC decoder 232 and/or an interleaver (not shown).
FIG. 2D depicts a flowchart describing operation of an example decoding circuit of a highly-spectrally-efficient OFDM receiver. The flowchart begins with block 272 in which a vector of C received physical subcarrier values arrive at decoding circuit 218 .
In block 274 , the best candidate vector is determined to a first level of confidence. For example, in block 274 , the best candidate vector may be determined based on a first number of iterations of a sequence estimation algorithm.
In block 276 , the controlled ISCI model may be applied to the best candidate vector determined in block 274 to generate reconstructed signal 227 a.
In block 278 , the best candidate vector is determined to a second level of confidence. For example, the best candidate determined in block 278 may be based on a second number of iterations of the sequence estimation algorithm, where the second number of iterations is larger than the first number of iterations.
In block 280 , the controlled ISCI model may be applied to the best candidate determined in block 278 to generate reconstructed signal 227 b.
In block 282 , coefficients used by the equalizer 212 are updated/adapted based on the reconstructed signal 227 b determined in block 280 .
In block 284 , subsequent received physical subcarrier values are equalized based on the coefficients calculated in block 282 .
Blocks 286 and 288 may occur in parallel with blocks 278 - 284 .
In block 286 , the carrier recovery loop 222 may determine frequency and/or phase error based on signal 227 a calculated in block 276 .
In block 288 , samples received during a subsequent OFDM symbol period may be frequency corrected based on the error determined in block 286 and/or subsequent received physical subcarrier values are phase corrected based on the error determined in block 286 .
In an example implementation, a first electronic device (e.g., 100), may map, using a selected modulation constellation, each of C′ bit sequences to a respective one of C′ symbols, where C′ is a number greater than one. The electronic device may process the C′ symbols to generate C′ inter-carrier correlated virtual subcarrier values. The electronic device may decimate the C′ virtual subcarrier values down to C physical subcarrier values, C being a number less than C′. The electronic device may transmit the C physical subcarrier values on C orthogonal frequency division multiplexed (OFDM) subcarriers. The transmission may be via a channel having a significant amount of nonlinearity. The significant amount of nonlinearity may be such that it degrades, relative to a perfectly linear channel, a performance metric in said receiver by less than 1 dB, whereas, in a full response communication system, it would degrade, relative to a perfectly linear channel, the performance metric by 1 dB or more. The processing may introduce a significant amount of aliasing such that the ratio of the signal power of the C′ virtual subcarrier values prior to the decimating to the signal power of the C physical subcarrier values after the decimating is equal to or less than a threshold signal to noise ratio of a receiver to which the OFDM subcarriers are transmitted (e.g., for a decimation by a factor of 2, P2 is the power in the upper half of the C′ virtual subcarrier values). The modulation constellation may be an N-QAM constellation, N being an integer. The bit sequences may be coded according to a forward error correction algorithm. The processing may comprise multiplication of C′ symbols by a C′×C′ matrix. Row or column length of the matrix may be an integer less than C′, such that the multiplication results in a decimation of the C′ symbols. The processing may seeks to achieve a target symbol error rate, target bit error rate, and/or target packet error rate in presence of additive white Gaussian noise and a dynamic frequency selective fading channel. The processing may comprises filtering the C′ symbols using an array of filter tap coefficients. The filtering may comprise cyclic convolution. The filtering may comprises multiplication by a circulant matrix populated with the filter tap coefficients. The filter tap coefficients may be selected to achieve one or more of: a target symbol error rate, a target bit error rate, and/or a target packet error rate in presence of one or more of: additive white Gaussian noise, dynamic frequency selective fading channel, and non-linear distortion. The filter tap coefficients may be selected based on signal-to-noise ratio (SNR) measurements fed back from a second electronic device that receives communications from the first electronic device.
The electronic device may receive a first message from a second electronic device. In response to the first message, the first electronic device may cease transmission of data on a particular one of the physical subcarriers. The electronic device may receive a second message from the second electronic device. In response to the second message, the first electronic device may resume transmission of data on the particular one of the physical subcarriers. Subsequent to the receiving the first message, and prior to receiving the second message, transmitting a pilot signal on the particular one of the physical subcarriers. The ceasing transmission of data on the particular one of the physical subcarriers may comprise one or more of: changing a value of the number C; and changing a value of the number C′. An OFDM symbol period for the transmitting may be approximately (C+Δ)/BW. Each of the C OFDM subcarriers has a bandwidth of approximately BW/(C+0), where BW is a bandwidth used for the transmitting, and A is the number of non-data-carrying subcarriers within the bandwidth BW. Prior to the transmitting, transforming the C physical subcarrier values to C+Δ+P time-domain samples using an inverse fast Fourier transform.
Other implementations may provide a non-transitory computer readable medium and/or storage medium, and/or a non-transitory machine readable medium and/or storage medium, having stored thereon, a machine code and/or a computer program having at least one code section executable by a machine and/or a computer, thereby causing the machine and/or computer to perform the processes as described herein.
Methods and systems disclosed herein may be realized in hardware, software, or a combination of hardware and software. Methods and systems disclosed herein may be realized in a centralized fashion in at least one computing system, or in a distributed fashion where different elements are spread across several interconnected computing systems. Any kind of computing system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computing system with a program or other code that, when being loaded and executed, controls the computing system such that it carries out methods described herein. Another typical implementation may comprise an application specific integrated circuit (ASIC) or chip with a program or other code that, when being loaded and executed, controls the ASIC such that is carries out methods described herein.
While methods and systems have been described herein with reference to certain implementations, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present method and/or system. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from its scope. Therefore, it is intended that the present method and/or system not be limited to the particular implementations disclosed, but that the present method and/or system will include all implementations falling within the scope of the appended claims.