(en)A microelectronic programmable structure suitable for storing information, a device including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

1.ApplicationNumber: US-76055607-A
1.PublishNumber: US-2008006812-A1
2.Date Publish: 20080110
3.Inventor: KOZICKI MICHAEL N.
BALAKRISHNAN MURALIKRISHNAN

4.Inventor Harmonized: KOZICKI MICHAEL N(US)
BALAKRISHNAN MURALIKRISHNAN(US)

5.Country: US
6.Claims:
(en)A microelectronic programmable structure suitable for storing information, a device including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

7.Description:
(en)CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation-in-part of application Ser. No. 11/744,382, entitled OPTIMIZED SOLID ELECTROLYTE FOR PROGRAMMABLE METALLIZATION CELL DEVICES AND STRUCTURES, filed May 4, 2007, which is a continuation-in-part of application Ser. No. 11/117,229, entitled PROGRAMMABLE STRUCTURE, AN ARRAY INCLUDING THE STRUCTURE, AND METHODS OF FORMING THE SAME, filed Aug. 28, 2005, which is a divisional application of application Ser. No. 10/390,268, entitled PROGRAMMABLE STRUCTURE, AN ARRAY INCLUDING THE STRUCTURE, AND METHODS OF FORMING THE SAME, and filed Mar. 17, 2003 which is a continuation-in-part of U.S. application Ser. No. 10/268,107, filed Oct. 9, 2002 entitled PROGRAMMABLE MICROELECTRONIC DEVICE, STRUCTURE, AND SYSTEM AND METHOD OF FORMING THE SAME, filed Oct. 9, 2002, which is a continuation-in-part of application Ser. No. 10/118,276 entitled MICROELECTRONIC DEVICE, STRUCTURE, AND SYSTEM, INCLUDING A MEMORY STRUCTURE HAVING A VARIABLE PROGRAMMABLE PROPERTY AND METHOD OF FORMING SAME, filed Apr. 9, 2002, which is a continuation-in-part of application Ser. No. 09/502,915, entitled PROGRAMMABLE MICROELECTRONIC DEVICES AND METHODS OF FORMING AND PROGRAMMING SAME, filed Apr. 19, 2000, and which is a continuation-in-part of application Ser. No. 09/951,882, entitled MICROELECTRONIC PROGRAMMABLE DEVICE AND METHODS OF FORMING AND PROGRAMMING THE SAME, filed Sep. 10, 2001 and claims priority to Application Ser. No. 60/798,096, entitled OPTIMIZED SOLID ELECTROLYTES FOR PROGRAMMABLE METALLIZATION CELL DEVICES, filed May 4, 2006.


FIELD OF INVENTION
The present invention generally relates to programmable microelectronic devices. More particularly, the invention relates to programmable microelectronic structures and devices having an electrical property that can be variably programmed by manipulating an amount of energy supplied to the structure during a programming function and to memory arrays including the structures.
BACKGROUND OF THE INVENTION
Memory devices are often used in electronic systems and computers to store information in the form of binary data. These memory devices may be characterized into various types, each type having associated with it various advantages and disadvantages.
For example, random access memory (“RAM”), which may be found in personal computers, is typically volatile semiconductor memory; in other words, the stored data is lost if the power source is disconnected or removed. Dynamic RAM (“DRAM”) is particularly volatile in that it must be “refreshed” (i.e., recharged) every few hundred milliseconds in order to maintain the stored data. Static RAM (“SRAM”) will hold the data after one writing so long as the power source is maintained; once the power source is disconnected, however, the data is lost. Thus, in these volatile memory configurations, information is only retained so long as the power to the system is not turned off. In general, these RAM devices can take up significant chip area and therefore may be expensive to manufacture and consume relatively large amounts of energy for data storage. Accordingly, improved memory devices suitable for use in personal computers and the like are desirable.
Other storage devices such as magnetic storage devices (e.g., floppy disks, hard disks and magnetic tape) as well as other systems, such as optical disks, CD-RW and DVD-RW are non-volatile, have extremely high capacity, and can be rewritten many times. Unfortunately, these memory devices are physically large, are shock/vibration-sensitive, require expensive mechanical drives, and may consume relatively large amounts of power. These negative aspects make such memory devices non-ideal for low power portable applications such as lap-top and palm-top computers, personal digital assistants (“PDAs”), and the like.
Due, at least in part, to a rapidly growing numbers of compact, low-power portable computer systems and hand-held appliances in which stored information changes regularly, low energy read/write semiconductor memories have become increasingly desirable and widespread. Furthermore, because these portable systems often require data storage when the power is turned off, non-volatile storage device are desired for use in such systems.
One type of programmable semiconductor non-volatile memory device suitable for use in such systems is a programmable read-only memory (“PROM”) device. One type of PROM, a write-once read-many (“WORM”) device, uses an array of fusible links. Once programmed, the WORM device cannot be reprogrammed.
Other forms of PROM devices include erasable PROM (“EPROM”) and electrically erasable PROM (EEPROM) devices, which are alterable after an initial programming. EPROM devices generally require an erase step involving exposure to ultra violet light prior to programming the device. Thus, such devices are generally not well suited for use in portable electronic devices. EEPROM devices are generally easier to program, but suffer from other deficiencies. In particular, EEPROM devices are relatively complex, are relatively difficult to manufacture, and are relatively large. Furthermore, a circuit including EEPROM devices must withstand the high voltages necessary to program the device. Consequently, EEPROM cost per bit of memory capacity is extremely high compared with other means of data storage. Another disadvantage of EEPROM devices is that, although they can retain data without having the power source connected, they require relatively large amounts of power to program. This power drain can be considerable in a compact portable system powered by a battery.
Various hand-held appliances such as PDAs, portable phones, and the like as well as other electronic systems generally include a memory device coupled to a microprocessor and/or microcontroller formed on a separate substrate. For example, portable computing systems include a microprocessor and one or more memory chips coupled to a printed circuit board.
Forming memory devices and the microprocessor on separate substrates may be undesirable for several reasons. For example, forming various types of memory on separate substrate may be relatively expensive, may require relatively long transmission paths to communicate between the memory devices and any associated electronic device, and may require a relatively large amount of room within a system. Accordingly, memory structures that may be formed on the same substrate as another electronic device and methods of forming the same are desired. Furthermore, this memory technology desirably operates at a relatively low voltage while providing high speed memory with high storage density and a low manufacturing cost.
SUMMARY OF THE INVENTION
The present invention provides improved microelectronic programmable devices, structures, and systems and methods of forming the same. More particularly, the invention provides programmable structures that can be variably programmed depending on an amount of energy used to program the device. Such structures can replace both traditional nonvolatile and volatile forms of memory and can be formed on the same substrate as and/or overlying another microelectronic device.
The ways in which the present invention addresses various drawbacks of now-known programmable devices are discussed in greater detail below. However, in general, the present invention provides a programmable device that is relatively easy and inexpensive to manufacture, which is relatively easy to program, and which can be variably programmed.
In accordance with one exemplary embodiment of the present invention, a programmable structure includes an ion conductor and at least two electrodes. The structure is configured such that when a bias is applied across two electrodes, one or more electrical properties of the structure change. In accordance with one aspect of this embodiment, a resistance across the structure changes when a bias is applied across the electrodes. In accordance with other aspects of this embodiment, a capacitance or other electrical property of the structure changes upon application of a bias across the electrodes. In accordance with a further aspect of this embodiment, an amount of change in the programmable property is manipulated by altering (e.g., thermally or electrically) an amount of energy used to program the device. One or more of these electrical changes and/or the amount of change may suitably be detected. Thus, stored information may be retrieved from a circuit including the structure.
In accordance with another exemplary embodiment of the invention, a programmable structure includes an ion conductor, at least two electrodes, and a barrier interposed between at least a portion of one of the electrodes and the ion conductor. In accordance with one aspect of this embodiment, the barrier material includes a material configured to reduce diffusion of ions between the ion conductor and at least one electrode. In accordance with another aspect, the barrier material includes an insulating or high-resistance material. In accordance with yet another aspect of this embodiment, the barrier includes material that conducts ions, but which is relatively resistant to the conduction of electrons.
In accordance with another exemplary embodiment of the invention, a programmable microelectronic structure is formed on a surface of a substrate by forming a first electrode on the substrate, depositing a layer of ion conductor material over the first electrode, and depositing conductive material onto the ion conductor material. In accordance with one aspect of this embodiment, a solid solution including the ion conductor and excess conductive material is formed by dissolving (e.g., via thermal and/or photodissolution) a portion of the conductive material in the ion conductor. In accordance with a further aspect, only a portion of the conductive material is dissolved, such that a portion of the conductive material remains on a surface of the ion conductor to form an electrode on a surface of the ion conductor material. In accordance with another aspect of this embodiment of the invention, a structure including a high-resistance region is formed by dissolving a portion of the electrode such that a portion of the ion conductor includes a high concentration of the electrode material and another portion of the ion conductor includes a low concentration of the electrode material, such that the portion of the ion conductor with a low concentration of the electrode material forms a high resistance region within the structure.
In accordance with another embodiment of the invention, a programmable structure is formed on a surface of a substrate. In accordance with one aspect of this embodiment, a programmable structure is formed as part of an integrated circuit.
In accordance with a further exemplary embodiment of the invention, multiple bits of information are stored in a single programmable structure. In accordance with one aspect of this embodiment, a programmable structure includes a floating electrode interposed between two additional electrodes.
In accordance with yet another embodiment of the invention, multiple programmable devices are coupled together using a common electrode (e.g., a common anode or a common cathode).
In accordance with yet a further exemplary embodiment of the present invention, a capacitance of a programmable structure is altered by causing ions within an ion conductor of the structure to migrate.
In accordance with yet another embodiment of the invention, a volatility of a memory cell in accordance with the present invention is manipulated by altering an amount of energy used during a write process for the memory. In accordance with this embodiment of the invention, higher energy is used to form nonvolatile memory, while lower energy is used to form volatile memory. Thus, a single memory device, formed on a single substrate, may include both nonvolatile and volatile portions. In accordance with a further aspect of this embodiment, the relative volatility of one or more portions of the memory may be altered at any time by changing an amount of energy supplied to a portion of the memory during a write process.
In accordance with additional embodiment of the invention, the structures include an additional conductive layer proximate one or more of the electrodes to improve the speed of the read/write process.
In accordance with yet another embodiment of the invention, pulse mode programming is used to read and write information. In this case, information can be retrieved from the device using a destructive read or a destructive write process.
In accordance with yet another embodiment of the invention, a programmable structure includes an additional electrode for sensing a state (0 or 1) of the programmable device.


BRIEF DESCRIPTION OF THE DRAWINGS
A more complete understanding of the present invention may be derived by referring to the detailed description and claims, considered in connection with the figures, wherein like reference numbers refer to similar elements throughout the figures, and:
FIGS. 1 and 2 are cross-sectional illustrations of a programmable structure formed on a surface of a substrate in accordance with the present invention;
FIGS. 3-5 are cross-sectional illustrations of a programmable structure in accordance with another embodiment of the present invention, illustrating phase-separated ion conductors;
FIGS. 6, 8 , and 9 are current-voltage diagrams illustrating current and voltage characteristics of the devices of the present invention;
FIGS. 7, 18 , 19 , and 25 - 27 illustrate arrays of programmable structures in accordance with the present invention;
FIGS. 10-14 illustrate programmable structures including barrier layers in accordance with exemplary embodiments of the invention;
FIG. 15 is a cross-sectional illustration of a programmable structure in accordance with yet another embodiment of the present invention;
FIGS. 16 and 17 are schematic illustrations of a portion of a memory device in accordance with an exemplary embodiment of the present invention;
FIGS. 20-24 are illustrations of programmable structures having an additional electrode for sensing a state of the structures;
FIGS. 28-30 are illustrations of programmable structures in accordance with additional embodiments of the invention;
FIG. 31 illustrates a resistance voltage diagram for an exemplary programmable structure; and
FIGS. 32-34 illustrate multi-layered memory elements in accordance with yet further exemplary embodiments.


Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
DETAILED DESCRIPTION
The present invention generally relates to programmable microelectronic structures and devices, to arrays including the structures and devices, and to methods of forming and using the devices and arrays.
FIGS. 1 and 2 illustrate programmable microelectronic structures 100 and 200 formed on a surface of a substrate 110 in accordance with an exemplary embodiment of the present invention. Structures 100 and 200 include electrodes 120 and 130 , an ion conductor 140 , and optionally include buffer or barrier layers or regions 155 and/or 255 .
Generally, structures 100 and 200 are configured such that when a bias greater than a threshold voltage (V T ), discussed in more detail below, is applied across electrodes 120 and 130 , the electrical properties of structure 100 change. For example, in accordance with one embodiment of the invention, as a voltage V≧V T is applied across electrodes 120 and 130 , conductive ions within ion conductor 140 begin to migrate and form a region 160 having an increased conductivity compared to the bulk ion conductor (e.g., an electrodeposit) at or near the more negative of electrodes 120 and 130 . As region 160 forms, the resistance between electrodes 120 and 130 decreases, and other electrical properties may also change.
In the absence of any barriers, which are discussed in more detail below, the threshold voltage required to grow region 160 from one electrode toward the other and thereby significantly reduce the resistance of the device is approximately a few hundred millivolts. If the same voltage is applied in reverse, region 160 will dissolve back into the ion conductor and the device will return to a high resistance state. In a similar fashion, an effective barrier height of a diode that forms between an ion conductor and an electrode can be reduced by growing region 160 ; thus current flow may be increased through the structure, even if the resistance of the structure is substantially the same.
Structures 100 and 200 may be used to store information and thus may be used in memory circuits. For example, structure 100 or other programmable structures in accordance with the present invention may suitably be used in memory devices to replace DRAM, SRAM, PROM, EPROM, EEPROM devices, or any combination of such memory. In addition, programmable structures of the present invention may be used for other applications where programming or changing of electrical properties of a portion of an electrical circuit are desired.
In accordance with various embodiments of the invention, the volatility of programmable memory (e.g., cell 100 or 200 ) can be manipulated by altering an amount of energy (e.g., altering time, current, voltage, thermal energy, and/or the like) applied during a write process. In the case where region 160 forms during a write process, the greater the amount of energy (having a voltage greater than the threshold voltage for the write process) applied during the write process, the greater the growth of region 160 and hence the less volatile the memory. Conversely, relatively volatile, easily erased memory can be formed by supplying relatively little energy to the cell. Thus, relatively volatile memory can be formed using the same or similar structures used to form nonvolatile memory, and less energy can be used to form the volatile/easily erased memory. Use of less energy is particularly desirable in portable electronic devices that depend on stored energy for operation. The volatile and nonvolatile memory may be formed on the same substrate and partitioned or separated from each other such that each partition is dedicated to either volatile or nonvolatile memory; or, an array of memory cells may be configured as volatile or nonvolatile memory using programming techniques, such that the configuration (i.e., volatile or nonvolatile) of the memory can be altered by changing an amount of energy supplied during programming the respective portions of the memory array.
Referring again to FIGS. 1 and 2 , substrate 110 may include any suitable material. For example, substrate 110 may include semiconductive, conductive, semiinsulative, insulative material, or any combination of such materials. In accordance with one embodiment of the invention, substrate 110 includes an insulating material 112 and a portion 114 including a microelectronic device formed using a portion of the substrate. Layer 112 and portion 114 may be separated by additional layers (not shown) such as, for example, layers typically used to form integrated circuits. Because the programmable structures can be formed over insulating or other materials, the programmable structures of the present invention are particularly well suited for applications where substrate (e.g., semiconductor material) space is a premium. In addition, forming a memory cell overlying a microelectronic device may be advantageous because such a configuration allows greater data transfer between an array of memory cells and the microelectronic device using, for example, conductive plugs formed within layers 112 and 150 .
Electrodes 120 and 130 may be formed of any suitable conductive material. For example, electrodes 120 and 130 may be formed of doped polysilicon material, metal, metal silicides, and metal nitrides.
In accordance with one exemplary embodiment of the invention, one of electrodes 120 and 130 is formed of a material including a metal that dissolves in ion conductor 140 when a sufficient bias (V≧VT) is applied across the electrodes (an oxidizable electrode) and the other electrode is relatively inert and does not dissolve during operation of the programmable device (an indifferent electrode). For example, electrode 120 may be an anode during a write process and be comprised of a material including copper that dissolves in ion conductor 140 and electrode 130 may be a cathode during the write process and be comprised of an inert material such as tungsten, nickel, molybdenum, platinum, metal silicides, noble metals, including platinum, ruthenium, irridium, and metal nitrides, including tungsten nitride, titanium nitride, and the like. Having at least one electrode formed of a material including a metal, which dissolves in ion conductor 140 facilitates maintaining a desired dissolved metal concentration within ion conductor 140 , which in turn facilitates rapid and stable region 160 formation within ion conductor 140 or other electrical property change during use of structure 100 and/or 200 . Furthermore, use of an inert material for the other electrode (cathode during a write operation) facilitates electrodissolution of any region 160 that may have formed and/or return of the programmable device to an erased state after application of a sufficient voltage.
During an erase operation, dissolution of any region 160 that may have formed preferably begins at or near the oxidizable electrode/region 160 interface. Initial dissolution of the region 160 at the oxidizable electrode/region 160 interface may be facilitated by forming structure 100 such that the resistance at the oxidizable electrode/region 160 interface is greater than the resistance at any other point along region 160 , particularly, the interface between region 160 and the indifferent electrode.
One way to achieve relatively low resistance at the indifferent electrode is to form the electrode of relatively inert, non-oxidizing material such as platinum. Use of such material reduces formation of oxides at the interface between ion conductor 140 and the indifferent electrode as well as the formation of compounds or mixtures of the electrode material and ion conductor 140 material, which typically have a higher resistance than ion conductor 140 or the electrode material.
Relatively low resistance at the indifferent electrode may also be obtained by forming a barrier layer between the oxidizable electrode (anode during a write operation) and the ion conductor, wherein the barrier layer is formed of material having a relatively high resistance. Exemplary high resistance materials are discussed in more detail below.
Reliable growth and dissolution of region 160 can also be facilitated by providing a roughened indifferent electrode surface (e.g., a root mean square roughness of greater than about 1 nm) at the electrode/ion conductor interface. The roughened surface may be formed by manipulating film deposition parameters and/or by etching a portion of one of the electrode or ion conductor surfaces. During a write operation, relatively high electrical fields form about the spikes or peaks of the roughened surface, and thus regions 160 are more likely to form about the spikes or peaks. As a result, more reliable and uniform changes in electrical properties for an applied voltage across electrodes 120 and 130 may be obtained by providing a roughed interface between the indifferent electrode (cathode during a write operation) and ion conductor 140 .
Oxidizable electrode material may have a tendency to thermally dissolve or diffuse into ion conductor 140 , particularly during fabrication and/or operation of structure 100 . The thermal diffusion is undesired because it may reduce the resistance of structure 100 and thus reduce the change of an electrical property during use of structure 100 .
To reduce undesired diffusion of oxidizable electrode material into ion conductor 140 and in accordance with another embodiment of the invention, the oxidizable electrode may include a metal intercalated in a transition metal sulfide or selenide material such as A x (MB 2 ) 1-x , where A is Ag or Cu, B is S or Se, M is a transition metal such as Ta, V, and Ti, and x ranges from about 0.1 to about 0.7. The intercalated material mitigates undesired thermal diffusion of the metal (Ag or Cu) into the ion conductor material, while allowing the metal to participate in region 160 growth upon application of a sufficient voltage across electrodes 120 and 130 . For example, when silver is intercalated into a TaS 2 film, the TaS 2 film can include up to about 67 atomic percent silver. The A x (MB 2 ) 1-x material is preferably amorphous to prevent undesired diffusion of the metal though the material. The amorphous material may be formed by, for example, physical vapor deposition of a target material comprising A x (MB 2 ) 1-x .
α-AgI is another suitable material for the oxidizable electrode. Similar to the A x (MB 2 ) 1-x material discussed above, α-AgI can serve as a source of Ag during operation of structure 100 —e.g., upon application of a sufficient bias, but the silver in the AgI material does not readily thermally diffuse into ion conductor 140 . AgI has a relatively low activation energy for conduction of electricity and does not require doping to achieve relatively high conductivity. When the oxidizable electrode is formed of AgI, depletion of silver in the AgI layer may arise during operation of structure 100 , unless excess silver is provided to the electrode. One way to provide the excess silver is to form a silver layer adjacent the AgI layer. When interposed between a layer of silver and ion conductor 140 , the AgI layer reduces thermal diffusion of Ag into ion conductor 140 , but does not significantly affect conduction of Ag during operation of structure 100 . In addition, use of AgI increases the operational efficiency of structure 100 because the AgI mitigates non-Faradaic conduction (conduction of electrons that do not participate in the electrochemical reaction).
As discussed in more detail below, in accordance with one embodiment of the invention, at least one electrode 120 and 130 is formed of material suitable for use as an interconnect metal. For example, electrode 130 may form part of an interconnect structure within a semiconductor integrated circuit. In accordance with one aspect of this embodiment, electrode 130 is formed of a material that is substantially insoluble in material comprising ion conductor 140 . Exemplary materials suitable for both interconnect and electrode 130 material include metals and compounds such as tungsten, nickel, molybdenum, platinum, metal silicides, and the like.
As noted above, programmable structures of the present invention may include one or more barrier or buffer layers 155 , 255 interposed between at least a portion of ion conductor 140 and one of the electrodes 120 , 130 . Layers 155 , 255 may include ion conductors such as Ag x O, Ag x S, Ag x Se, Ag x Te, where x≧2, Ag y I, where x≧1, CuI 2 , CuO, CuS, CuSe, CuTe, GeO 2 , Ge z S 1-z , Ge z Se 1-z , Ge z Te 1-z , As z S 1-z , As z Se 1-z , As z Te 1-z , where z is greater than or equal to about 0.1, and combinations of these materials) interposed between ion conductor 140 and a metal layer such as silver.
Other materials suitable for buffer layers 155 and/or 255 include GeO 2 . Amorphous GeO 2 is relatively porous an will “soak up” silver during operation of device 100 , but will retard the thermal diffusion of silver to ion conductor 140 , compared to structures or devices that do not include a buffer layer.
Buffer layers can also be used to increase the off resistance and “write voltage” by placing a high-resistance buffer layer (e.g., GeO 2 , air, a vacuum, or the like) between ion conductor 140 and the indifferent electrode. In this case, the high-resistance buffer material allows metal such as silver to diffuse though or plate across the buffer and take part in the electrochemical reaction.
When the barrier layer between the indifferent electrode and the ion conductor includes a high resistance material, the barrier may include ions that contribute to electrodeposit growth or the barrier may be devoid of ions. In either case, the barrier must be able to transmit electrons, by conduction or tunneling, such that the redox reaction occurs, allowing for region 160 growth.
In some cases, an electrodeposit may form within the high-resistance barrier layer. Exemplary high-resistance barrier layers that support electrodeposit growth include gas-filled or vacuum gap regions, porous oxide films, of other high-resistance glassy materials, and semiconductor material as long as the barrier is thin enough to allow electron tunneling from the cathode to the ion conductor at reasonable voltages (e.g., less than or equal to about 1 volt), can support electron transport, and can allow ions to be reduced within the barrier material volume.
Layers 155 and/or 255 may also include a material that restricts migration of ions between conductor 140 and the electrodes. In accordance with exemplary embodiments of the invention, a barrier layer includes conducting material such as titanium nitride, titanium tungsten, a combination thereof, or the like. The barrier may be electrically indifferent, i.e., it allows conduction of electrons through structure 100 or 200 , but it does not itself contribute ions to conduction through structure 200 . An electrically indifferent barrier may reduce undesired electrodeposit growth during operation of the programmable device, and thus may facilitate an “erase” or dissolution of region 160 when a bias is applied which is opposite to that used to grow region 160 . In addition, use of a conducting barrier allows for the “indifferent” electrode to be formed of oxidizable material because the barrier prevents diffusion of the electrode material to the ion conductor.
Ion conductor 140 is formed of material that conducts ions upon application of a sufficient voltage. In general, ion conductors in accordance with the present invention can conduct ions without requiring a phase change, can conduct ions at a relatively low temperature (e.g., below 125° C.), can conduct ions at relatively low electrical currents, have a relatively high transport number, and exhibit relatively high ion conductivity.
Ion conductor 140 may also suitably include dissolved conductive material. For example, ion conductor 140 may comprise a solid solution that includes dissolved metals and/or metal ions. In accordance with one exemplary embodiment of the invention, conductor 140 includes metal and/or metal ions dissolved SiO x . In addition, conductor 140 may include network modifiers that affect mobility of ions through conductor 140 . For example, materials such as metals (e.g., silver), halogens, halides, or hydrogen may be added to conductor 140 to enhance ion mobility and thus increase erase/write speeds of the structure. Furthermore, as discussed in more detail below, ion conductor 140 may include a plurality of regions having different resistance values—for example, ion conductor 140 may include a first region proximate the oxidizable electrode having a relatively low resistance and a second region proximate the indifferent electrode having a relatively high resistance. By way of particular example, ion conductor 140 includes silicon dioxide
Ion conductor 140 may also include a filler material, which fills interstices or voids. Suitable filler materials include non-oxidizable and non-silver based materials such as a non-conducting, immiscible silicon nitride, having a cross-sectional dimension of less than about 1 nm, which do not contribute to the growth of region 160 . In this case, the filler material is present in the ion conductor at a volume percent of up to about 5 percent to reduce a likelihood that a region 160 will spontaneously dissolve into the supporting ternary material as the device is exposed to elevated temperature, which leads to more stable device operation without compromising the performance of the device. Ion conductor 140 may also include filler material to reduce an effective cross-sectional area of the ion conductor. In this case, the concentration of the filler material, which may be the same filler material described above but having a cross-sectional dimension up to about 50 nm, is present in the ion conductor material at a concentration of up to about 50 percent by volume.
As noted above, in accordance with various embodiments of the invention, ion conductor 140 includes silicon oxide (SiO x ), which may be deposited onto other material layers, and dissolved copper. Use of deposited oxides may be desirable because processes used to form the layer are compatible with, for example back end of line (BEOL) processing used in CMOS manufacturing. The silicon oxide may be deposited using, for example, physical vapor deposition and/or chemical vapor deposition. Combining oxide deposition with copper deposition and dispersion into the silicon oxide provides a relatively inexpensive solid electrolyte that can be readily integrated with circuits, such as CMOS circuits.
FIGS. 3-5 illustrate portions of programmable structures, which include phase-separated ion conductor material, in accordance with various embodiments of the present invention. FIG. 3 illustrates a phase-separated ion conductor region 302 , including a high-resistance portion 304 and low-resistance portions 306 . It is thought that phase-separated ion conductors facilitate large off resistance and high switching speed of programmable devices such as device 100 . The reason for this is that the metal ions from the soluble electrode will migrate within region 304 to bridge low-resistance regions 306 . Reduction of metal ions preferentially occurs in high-resistance regions 304 because the local field is highest in this area of ion conductor 302 . This process is relatively fast because a typical gap between low-resistance portions is on the order of about 1 nm or less.
FIG. 4 illustrates a structure 400 , including a phase-separated ion conductor 402 . Ion conductor 402 includes high-resistance portions 404 and low-resistance portions 406 . Portions 404 and 406 may be formed of corresponding high-resistance and low-resistance material described above in connection with portions 304 and 306 . Structure 400 may be formed by sequentially depositing high-resistivity material and low-resistance material. Although illustrated with only two high-resistance portions and two low-resistance portions, structures in accordance with the present invention may include any desired number of low and high-resistivity portions.
Similar to the operation of structure 300 , the operation speed of structure 400 is primarily limited by the change of resistance of high-resistance portions 404 . Accordingly, operational speed of structures 400 can be manipulated by altering a thickness of layer(s) 404 .
FIG. 5 illustrates another structure 500 , which includes phase separated ion conductor material 502 . Structure 500 is similar to structures 300 and 400 , except that structure 500 includes particles 508 , including a high-resistance portion 504 and a low-resistance portion 506 , which may be formed of low and high-resistance materials described herein.
Referring again to FIGS. 1 and 2 , in accordance with one exemplary embodiment of the invention, at least a portion of structure 100 is formed within a via of an insulating material 150 . Forming a portion of structure 100 within a via of an insulating material 150 may be desirable because, among other reasons, such formation allows relatively small structures, e.g., on the order of 10 nanometers, to be formed. In addition, insulating material 150 facilitates isolating various structures 100 from other electrical components.
Insulating material 150 suitably includes material that prevents undesired diffusion of electrons and/or ions from structure 100 . In accordance with one embodiment of the invention, material 150 includes silicon nitride, silicon oxynitride, polymeric materials such as polyimide or parylene, or any combination thereof.
A contact 165 may suitably be electrically coupled to one or more electrodes 120 , 130 to facilitate forming electrical contact to the respective electrode. Contact 165 may be formed of any conductive material and is preferably formed of a metal, alloy, or composition including aluminum, tungsten, or copper.
In accordance with one embodiment of the invention, structure 100 is formed by forming electrode 130 on substrate 110 . Electrode 130 may be formed using any suitable method such as, for example, depositing a layer of electrode 130 material, patterning the electrode material, and etching the material to form electrode 130 . Insulating layer 150 may be formed by depositing insulating material onto electrode 130 and substrate 110 and forming vias in the insulating material using appropriate patterning and etching processes. Ion conductor 140 and electrode 120 may then be formed within insulating layer 150 by depositing ion conductor 140 material and electrode 120 material within the via. Such ion conductor and electrode material deposition may be selective—i.e., the material is substantially deposited only within the via, or the deposition processes may be relatively non-selective. If one or more non-selective deposition methods are used, any excess material remaining on a surface of insulating layer 150 may be removed using, for example, chemical mechanical polishing and/or etching techniques. Barrier layers 155 and/or 255 may similarly be formed using any suitable deposition and/or etch processes.
A solid solution suitable for use as ion conductor 140 may be formed in a variety of ways. For example, the solid solution may be formed by depositing a layer of conductive material such as metal over a deposited silicon oxide layer and exposing the metal and oxide to thermal and/or photo dissolution processing. In accordance with one exemplary embodiment of the invention, a solid solution of silicon oxide and copper is formed by depositing silicon oxide onto a substrate (or material layer), depositing a thin film of Cu onto the SiO x , and exposing the films to light having energy greater than the optical gap of the SiO x . If desired, network modifiers may be added to conductor 140 during deposition of conductor 140 (e.g., the modifier is in the deposited material or present during conductor 140 material deposition) or after conductor 140 material is deposited (e.g., by exposing conductor 140 to an atmosphere including the network modifier).
One of the electrodes may be formed during ion conductor 140 doping by depositing sufficient metal onto an ion conductor material and applying sufficient electrical or thermal energy to the layers such that a portion of the metal is dissolved within the ion conductor material and a portion of the metal remains on a surface of the ion conductor to form an electrode (e.g., electrode 120 ). Regions of differing conductivity within ion conductor 140 can be formed using this technique by applying a sufficient amount of energy to the structure such that a first portion of the ion conductor proximate the soluble electrode contains a greater amount of conductive material than a second portion of the ion conductor proximate the indifferent electrode. This process is self limiting if ion starting ion conductor layer is thick enough so that a portion of the film becomes saturated and a portion of the film is unsaturated.
In accordance with alternative embodiments of the invention, solid solutions containing dissolved metals may be directly deposited onto substrate 110 and the electrode then formed overlying the ion conductor. For example, a source including both ion conductor and conductive material can be used to form ion conductor 140 using physical vapor deposition or similar techniques.
An amount of conductive material such as metal dissolved in an ion conducting material such as chalcogenide may depend on several factors such as an amount of metal available for dissolution and an amount of energy applied during the dissolution process. However, when a sufficient amount of metal and energy are available for dissolution in chalcogenide material using photodissolution, the dissolution process is thought to be self limiting, substantially halting when the metal cations have been reduced to their lowest oxidation state.
Referring now to FIGS. 32-34 , structures, e.g., structures 3202 of device 3200 , 3300 , and 3400 can be integrated with integrated circuit metal line, e.g., lines 3204 - 3210 , which may correspond to metal 1 , 2 , 3 , and 4 lines.
By way of one example, structure 3202 is formed by depositing a thin film (e.g., <50 nm) of silicon oxide using PVD (e.g., reactive sputter/Si in an oxygen environment) or CVD (e.g., plasma enhanced) into vias within a silicon nitride dielectric layers 3212 , 3214 . The thickness of the silicon oxide layer is typically between about 1 and 100 nm, with about 10 to about 50 nm being an exemplary range. The vias within the silicon nitride provide electrical connectivity to underlying electrodes (e.g., tungsten electrodes) 3204 . A film of copper is then deposited and partially driven into the oxide using an inert (e.g., N 2 or Ar), reducing (e.g., hydrogen), or vacuum ambient anneal at about 200° C. to about 800° C. (e.g., about 610° C.) for about 1 to about 60 minutes (e.g., 15 minutes) and UV light of about 0.1 to 1 J/cm 2 total energy. The copper layer may be about 1 to about 100 nm, with about 10 to about 25 nm being an exemplary range. Structure 3200 may also include a capping electrode formed of, e.g., copper, and optionally a suitable barrier.
Device 3300 is similar to device 3200 , except device 3300 includes back-to-back structures 3202 , formed in dielectric layers 3302 , 3304 . Device 3400 is also similar to device 3200 , except device 3400 includes programmable structures 3402 , formed between metal 1 ( 3204 ) and metal 2 ( 3404 ) , metal 2 ( 3404 ) and metal 3 ( 3406 ), and metal 3 ( 3406 ) and metal 4 ( 3408 ) lines. As illustrated, devices 3200 - 3400 may also include conductive plugs (e.g., tungsten plugs) 3216 and partial plugs 3218 .
Information may be stored using programmable structures of the present invention by manipulating one or more electrical properties of the structures. For example, a resistance of a structure may be changed from a “0” or off state to a “1” or on state during a suitable write operation. Similarly, the device may be changed from a “1” state to a “0” state during an erase operation. In addition, as discussed in more detail below, the structure may have multiple programmable states such that multiple bits of information are stored in a single structure.
Write Operation
FIG. 6 illustrates current-voltage characteristics of a programmable structure (e.g. structure 200 ). Current through structure 200 in an off state (curve 610 ) begins to rise upon application of a bias of over about one volt; however, once a write step has been performed (i.e., an electrodeposit has formed), the resistance through conductor 140 drops significantly (i.e., to about 200 ohms), illustrated by curve 620 in FIG. 6 . As noted above, when electrode 130 is coupled to a more negative end of a voltage supply, compared to electrode 120 , a conductive region begins to form near electrode 130 and grow toward electrode 120 . An effective threshold voltage (i.e., voltage required to cause growth of the conductive region and to break through barrier 255 , thereby coupling electrodes 120 , 130 together) is relatively high because of barrier 255 . In particular, a voltage V≧V T must be applied to structure 200 sufficient to cause electrons to tunnel through barrier 255 (when barrier 255 comprises an insulating layer) to form the conductive region and to overcome the barrier (e.g., by tunneling through or leakage) and conduct through conductor 140 and at least a portion of barrier 255 .
In accordance with alternate embodiments of the invention, where no insulating barrier layer is present, an initial “write” threshold voltage is relatively low because no insulative barrier is formed between, for example, ion conductor 140 and either of the electrodes 120 , 130 .
As noted above, the relative volatility of the memory structures of the present invention may be altered by applying different amounts of energy to the structures during a write process. For example, a relatively high current pulse of a few hundred microamperes for a period of about several hundred nanoseconds may be applied to the structures illustrated in FIGS. 1 and 2 to form a relatively nonvolatile memory cell. Alternatively, the same current may be supplied to the same or similar memory structure for a shorter amount of time, e.g., several nanoseconds to form a relatively volatile memory structure. In either case, the memory of the present invention can be programmed at relatively high speeds and even the “volatile” memory is relatively nonvolatile compared to traditional DRAM. For example, the volatile memory may operate at speed comparable to DRAM and only require refreshing every several hours.
Read Operation
A state of a memory cell (e.g., 1 or 0) may be read, without significantly disturbing the state, by, for example, applying a forward or reverse bias of magnitude less than a voltage threshold (about 1.4 V for a structure illustrated in FIG. 6 ) for electrodeposition or by using a current limit which is less than or equal to the minimum programming current (the current which will produce the highest of the “on” resistance values). A current limited (to about 1 milliamp) read operation is illustrated in FIG. 6 . In this case, the voltage is swept from 0 to about 2 V and the current rises up to the set limit (from 0 to 0.2 V), indicating a low resistance (ohmic/linear current-voltage) “on” state. Another way of performing a non-disturb read operation is to apply a pulse, with a relatively short duration, which may have a voltage higher than the electrochemical deposition threshold voltage such that no appreciable Faradaic current flows, i.e., nearly all the current goes to polarizing/charging the device and not into the electrodeposition process.
In accordance with various embodiments of the invention, circuits including the programmable structures include temperature compensation devices to mitigate effects of temperature variation on the performance of the programmable device. One exemplary temperature compensation circuit includes a programmable structure having a known erased state. In this case, during a read operation, a progressively increasing voltage is applied to a programmable structure having an unknown state as well as to the structure having the known erased state. If the unknown structure has been written to, it will switch on before the known erased device and if the unknown structure is in an erased state, the two devices will switch on at approximately the same time. Alternatively, a temperature compensation circuit can be used to produce a comparison voltage or current to be compared to a voltage or current produced by a programmable structure of an unknown state during a read process.
Erase Operation
A programmable structure (e.g., structure 200 ) may suitably be erased by reversing a bias applied during a write operation, wherein a magnitude of the applied bias is equal to or greater than the threshold voltage for electrodeposition in the reverse direction. In accordance with an exemplary embodiment of the invention, a sufficient erase voltage (V≧V T ) is applied to structure 200 for a period of time, which depends on energy supplied during the write operation, but is typically less than about 1 millisecond to return structure 200 to its “off” state having a resistance well in excess of a million ohms. In cases where the programmable structure does not include a barrier between conductor 140 and electrode 120 , a threshold voltage for erasing the structure is much lower than a threshold voltage for writing the structure because, unlike the write operation, the erase operation does not require electron tunneling through a barrier or barrier breakdown.
Referring to FIGS. 32-34 , voltage sweeps from −1V to 2V to −1V were performed on structures 3202 and device current and resistance were measured. Unwritten and fully-erased devices of 500 nm to 1 μm in diameter transitioned from a high resistance state in excess of 10 MΩ to their on sate at 1.5 C, and the erase was initiated at −0.5V. The on resistance was a function of current limit: a 500 nm structure programmed at 1 μA, 10 μA, 100 μA, and 1 mA (with no erase performed inbetween) yielded states of 2.03 MΩ, 35.3 MΩ, 1.48 MΩ, and 294 Ω respectively. No upward shift in resistivity was evident beyond 10 5 for devices programmed at 10 μA and read at 300 mV.
Pulse Mode Read/Write
In accordance with an alternate embodiment of the invention, pulse mode programming is used to write to and read from a programmable structure. In this case, similar to the process described above, region 160 forms during a write process; however, unlike the process described above, at least a portion region 160 is removed or dissolved during a read operation. During an erase/read process, the magnitude of the current pulse is detected to determine the state (1 or 0) of the device. If the device had not previously been written to or has previously been erased, no ion current pulse will be detected at or above the reduction/oxidation potential of the structure. But, if the device is in a written state, an elevated current will be detected during the destructive read/erase step. Because this is a destructive read operation, information must be written to each structure after each read process—similar to DRAM read/write operations. However, unlike DRAM devices, the structures of the present invention are stable enough to allow a range of values to be stored (e.g., various amounts of region 160 ). Thus, a partially destructive read that decrease, but does not completely eliminate region 160 , can be used. In accordance with an alternate aspect of this embodiment, a destructive write process rather than a destructive erase process can be used read the device. In this case, if the cell is in an “off” state, a write pulse will produce an ion current spike as region 160 forms, whereas a device that already includes a region 160 will not produce the ion current spike if the process has been limited by a lack of oxidizable silver.
FIG. 7 illustrates an array 700 of programmable structure 702 - 708 that form rows R 1 -R 3 and column C 1 -C 3 of programmable structures. When pulse-mode programming is employed to read and write to array 700 , addition diodes and transistors typically used for structure isolation, are not required, so long as regions 160 of the structures are not grown to an extent that they short the structure. A non-bridging region can be obtained by using limited write times, limiting an amount of oxidizable material at the oxidizable electrode that can contribute to region 160 formation, and/or using a resistive region between the electrodes that allows sufficient electron current, but prevents or decreases electrodeposition throughout ion conductor 140 .
In array 700 , a non-bridging region 160 is grown in the selected structure by, for example, biasing C 2 =+V t /2, R 2 =−V t /2, where V t is the reduction/oxidation potential, with all other rows and columns held at or near zero volts, so that no other device in the array sees the full forward write voltage. The resistance remains high after writing as the electrodeposit (region 160 ) does not bridge the electrodes. The read/erase bias is C 2 =−V t /2, R 2 =+V t /2 with all others held at zero volts. If the device is in the “off” state and the erase pulse is applied, very little current will flow through the high resistance electrolyte. If, however, a partial electrodeposit has been formed by a write operation, an erase pulse will produce an ion current spike through C 2 and R 2 as the electrodeposited metal is oxidized and re-plated on the negative electrode (the oxidizable anode in the write process). This current spike can be sensed and therefore the state of the selected cell can be determined by this process. Note that it is also possible to use full rather than half or partial voltages when the non-selected rows and columns are allowed to float (via the use of tri-state drivers); e.g., C 2 =+V t and R 2 =0 for write, C 2 =0 and R 2 =+V t for read/erase.
Control of Operational Parameters
The concentration of conductive material in the ion conductor can be controlled by applying a bias across the programmable device. For example, metal such as silver may be taken out of solution by applying a negative voltage in excess of the reduction potential of the conductive material. Conversely, conductive material may be added to the ion conductor (from one of the electrodes) by applying a bias in excess of the oxidation potential of the material. Thus, for example, if the conductive material concentration is above that desired for a particular device application, the concentration can be reduced by reverse biasing the device to reduce the concentration of the conductive material. Similarly, metal may be added to the solution from the oxidizable electrode by applying a sufficient forward bias. Additionally, it is possible to remove excess metal build up at the indifferent electrode by applying a reverse bias for an extended time or an extended bias over that required to erase the device under normal operating conditions. Control of the conductive material may be accomplished automatically using a suitable microprocessor.
With particular reference to FIGS. 3-5 , a partial write or a partial erase caused by a forward or reverse programming pulse of insufficient duration and/or current to introduce enough silver to significantly reduce the resistance of the high-resistance regions will cause additional silver to migrate from the soluble electrode the high-resistance portions. The conductivity and activation energy in these zones are altered by this excess silver even though the device will appear to be in a high resistance state. The change in activation energy results in higher ion mobility and hence this partial preprogramming results in much faster switching than in a device which had been fully written or erased, which in turn allows appropriately scaled devices to operate at SRAM speeds (in the nanosecond or less range).
In addition, in a written device that has “faded” due to thermal diffusion of the electrodeposited material away from the low resistance pathway, the local excess silver will still promote a lower activation energy but in this case, there is also sufficient silver present that the voltage required to reform the conducting link will be lower than in the case of a normal write. The “reclosure” voltage will be several tens of mV lower than the normal write threshold potential of the system since the silver required to close the link is already in the material and does not have to be released from the oxidizable electrode. This means that a simple “read” operation involving a short pulse below the write threshold potential will be sufficient to regenerate a faded on-state in the device but will be insufficient to disturb a device that has been fully erased (and hence does not have the excess silver). This will allow faded lightly written (low programming current) states to be automatically regenerated by the read operation, thereby extending the effective retention of the devices.
This technique may also be used to form one of the electrodes from material within the ion conductor material. For example, silver from the ion conductor may be plated out to form the oxidizable electrode. This allows the oxidizable electrode to be formed after the device is fully formed and thus mitigates problems associated with conductive material diffusing from the oxidizable electrode during manufacturing of the device.
The threshold voltage of programmable devices may be manipulated in accordance with various embodiments of the present invention. Manipulation of the threshold voltage allows configuration of the programmable devices for desired read and write voltages. In general, as noted above, the threshold voltage depends on, among other things, an amount of conductive material present in the ion conductor and/or any barrier.
One way to manipulate the electrodeposition threshold voltage is to manipulate the conductive material dispersed within the ion conductor material. Another technique for manipulating the threshold voltage is to alter an amount of oxidizable material at or near the indifferent electrode. In this case, the oxidizable metal at the cathode can be altered by first forming an electrodeposit at or near the indifferent electrode and then applying a reverse bias sufficient to dissolve a portion of the electrodeposit. The threshold voltage generally goes down as the amount of oxidizable metal at the cathode goes up. Alternatively, a write process may be used to form a desired electrodeposit at or near the cathode. This electrochemical control of the threshold voltage can be used to heal or regenerate an electrodeposit that has been thermally or electrochemically damaged or redistributed.
Therefore, a read operation can be used to automatically re-electrodeposit the silver and regenerate the data state stored in the device via the electrodeposited material. This will ensure that the programmable structures effectively retain data for extended periods of time.
Another technique for manipulating threshold voltage is by forming a layer of material between the indifferent electrode and the ion conductor layer, wherein the layer of material is capable of conducting ions and forming an electrodeposit and has a lower concentration of oxidizable material than the ion conductor. Exemplary materials suitable for this layer include undoped or doped ion conductor materials that have a low solubility level for the oxidizable material. The material layer between the indifferent electrode and the ion conductor reduces oxidizable material build up neat the indifferent electrode during processing and operation of the programmable structure.
An example of a write operation on a device which includes a saturated sulfur-ion conductor and a layer of relatively low conductive material content, less than 10 nm thick, between the indifferent electrode and the saturated ion conductor is illustrated in FIG. 8 (current vs. voltage for a 1 μA programming current) and FIG. 9 (resistance vs. voltage for a 1 μA programming current).
FIGS. 10 and 11 illustrate additional structures, which are configured to mitigate any unwanted diffusion of conductive material within an ion conductor, in accordance with further exemplary embodiments of the present invention. In general, the structures illustrated in FIGS. 10 and 11 include a relatively narrow ion conductor (compared to the height of the ion conductor) surrounded by a material which is less ion conductive than the ion conductor.
Structure 900 includes a first electrode 902 , an insulating layer 904 , a diffusion barrier 906 , an ion conductor 908 and a second electrode 910 . Electrodes 902 and 910 , insulating layer 904 , and ion conductor 908 may be formed of the corresponding materials and using the same techniques described above in connection with FIGS. 1 and 2 . The barriers may be configured such that only one “column” of ion conductor material spans between the electrodes or the structures may include a plurality of ion conductor columns that span between the electrodes. In the latter case, the electrodeposition may only occur in one of the columns if the current is appropriately limited. In either case, because the column diameter is relatively small (e.g., less than about 50 nm) the current required to saturate the region is also relatively small (e.g., about 30 μA)
Diffusion barrier 906 can be formed by conformally depositing a barrier material 1002 such as silicon nitride or any of the barrier materials discussed above in connection with layer 155 and 255 and illustrated in FIG. 11 and removing a portion of the barrier material (e.g., using an anisotropic etch) to form barrier 906 illustrated in FIG. 10 . Ion conductor 908 can then be formed using deposition and etch or damascene techniques.
Another technique for forming diffusion barriers is illustrated in FIGS. 12 and 13 . In this case, porous barrier material 1102 is formed on a surface of a substrate 1104 and ion conductor material is formed in the porous regions of barrier material 1102 . Alternatively, porous material 1102 can be used as an etch mask to etch ion conductor material (using an anisotropic etch) to form columns of ion conductor material. Spaces between to columns are then filled with appropriate barrier materials such as silicon nitride. Electrodes may be formed about one or more columns of ion conductor material as described herein to form programmable devices of the present invention.
FIG. 14 illustrates yet another structure 1300 suitable for forming diffusion-resistant programmable structures. Structure 1300 includes a first electrode 1302 , a second electrode 1304 , an ion conductor 1306 , and a material layer 1308 (e.g., SiO2) that favors electrodeposit growth substantially in only one direction. Electrodes 1302 and 1304 and ion conductor 1306 may be formed of any of the corresponding electrodes and ion conductors described herein. In accordance with one aspect of this embodiment of the invention, layer 1308 is formed between ion conductor 1306 and the indifferent electrode.
As noted above, in accordance with yet another embodiment of the invention, multiple bits of data may be stored within a single programmable structure by controlling a size of region 160 , which is formed during a write process. A size of region 160 that forms during a write process depends on a number of coulombs or charge supplied to the structure during the write process, and may be controlled by using a current limit power source. In this case, a resistance of a programmable structure is governed by Equation 1, where R on is the “on” state resistance, V T is the threshold voltage for electrodeposition, and I LIM is the maximum current allowed to flow during the write operation.
R on = V T XXXX I LIM Equation ⁢ ⁢ 1

In practice, the limitation to the amount of information stored in each cell will depend on how stable each of the resistance states is with time. For example, if a structure with a programmed resistance range of about 3.5 kΩ and a resistance drift over a specified time for each state is about ±250 Ω, about 7 equally sized bands of resistance (7 states) could be formed, allowing 3 bits of data to be stored within a single structure. In the limit, for near zero drift in resistance in a specified time limit, information could be stored as a continuum of states, i.e., in analog form.
A portion of an integrated circuit 1402 , including a programmable structure 1400 , configured to provide additional isolation from electronic components is illustrated in FIG. 15 . Structure 1400 includes electrodes 1420 and 1430 , an ion conductor 1440 , a contact 1460 , and an amorphous silicon diode 1470 , such as a Schottky or p-n junction diode, formed between contact 1460 and electrode 1420 . Rows and columns of programmable structures 1400 may be fabricated into a high density configuration to provide extremely large storage densities suitable for memory circuits. In general, the maximum storage density of memory devices is limited by the size and complexity of the column and row decoder circuitry. However, a programmable structure storage stack can be suitably fabricated overlying an integrated circuit with the entire semiconductor chip area dedicated to row/column decode, sense amplifiers, and data management circuitry (not shown) since structure 1400 need not use any substrate real estate. In this manner, storage densities of many gigabits per square centimeter can be attained using programmable structures of the present invention. Utilized in this manner, the programmable structure is essentially an additive technology that adds capability and functionality to existing semiconductor integrated circuit technology.
FIG. 16 schematically illustrates a portion of a memory device including structure 1400 having an isolating p-n junction 1470 at an intersection of a bit line 1510 and a word line 1520 of a memory circuit. FIG. 17 illustrates an alternative isolation scheme employing a transistor 1610 interposed between an electrode and a contact of a programmable structure located at an intersection of a bit line 1610 and a word line 1620 of a memory device.
FIG. 18 illustrates another array 1800 , including programmable structures 1802 - 1808 and Zener diodes (preferably with low reverse turn on voltage) 1810 - 1816 , in accordance with the present invention. A selected cell is written by, for example, making C 2 =+V w /2, R 2 =−V w /2 (where V w is greater than or equal to the write threshold of the device) with all other rows and columns held at zero volts so that no other device in the array sees the full forward write voltage. To erase the selected cell, C 2 is set to −V E /2, R 2 =+V E /2 (where V E is greater than or equal to the reverse turn-on voltage of the Zener diode plus the erase threshold of the device) with all other rows and columns again held at zero volts. The selected device is read using much the same approach by making C 2 =+V R /2, R 2 =−V R /2 (where V R is chosen to be below the write threshold) with all other rows and columns held at zero volts. It is also possible to use full rather than half voltages when the non-selected rows and columns are allowed to float (via the use of tri-state drivers); e.g., C 2 =+V w and R 2 =0 for write, C 2 =0 and R 2 =+V E for erase, and C 2 =+V R and R 2 =0 for read.
FIG. 19 illustrates another array 1900 that uses structures 1902 - 1908 , which store information in the form of a change in capacitance rather than a change in resistance. This may be accomplished by the growth of a non-shorting electrodeposit, i.e., one that does not extend all the way from anode to cathode. A non-shorting electrodeposit can be the result of a reduced charge write pulse which produces a deposit that only extends a short distance from the cathode. A dielectric/tunnel barrier that allows sufficient electron current to flow into the electrolyte but which prevents electrodeposition across the structure can also be used to prevent a shorting electrodeposit from forming.
The capacitive storage structures 1902 - 1908 can be placed in an array without diodes or other isolation devices as they will not create shorting paths from one row or column to another. Structures 1902 - 1908 are programmed in the same way as the diode array described above, but the erase voltage is now just the threshold voltage for dissolution of the electrodeposit.
FIGS. 20-23 illustrate, schematically, another technique for storing information in an array of lateral programmable structures that include an additional sensing electrode. Each structure includes an anode 2002 , a cathode 2004 , a sense electrode 2006 , and a connector 2008 . Information is stored as the capacitance of the geometric overlap of the electrodeposit and sense electrode 2006 , separated from each other by an appropriate dielectric. In this case, anode 2002 and cathode 2004 in each device are fed by a row and column in the array. Since the electrodes are coplanar in a lateral PMC device, one of the electrodes (e.g., the anode) must be connected to the array by way of a via contact or connector 2008 through the inter-metal dielectric. FIGS. 20-23 each illustrate examples of individual device configuration schematics in which the anode is connected to a level 3 column (sense is level 1) ( FIG. 20 ) or a level 1 column (sense is level 3) ( FIG. 22 ). Configurations illustrated in FIGS. 21 and 23 have the sense line as a level 1 or level 3 offset row (under or over the electrolyte) with the other electrodes configured as before. The cathode is a level 2 row in all cases (the dielectrics are not shown and the devices are not drawn to scale).
FIGS. 24 and 25 illustrate another array 2400 formed using the configurations presented in either FIG. 20 or FIG. 22 . As illustrated in FIG. 25 , a selected cell 2502 is written and erased via R 2 and C 2 as described above, but is read by detecting a capacitance between R 2 and C 2 *.
Another approach to forming a passive programmable array is to form an incomplete or otherwise high resistance electrodeposit to produce an “on” state with a resistance which is high enough to prevent sneak paths. This may be achieved using a two terminal structure illustrated in FIG. 19 or three terminal structure illustrated in FIGS. 20-23 .
FIG. 26 illustrates a two-terminal structure array 2600 in which a partial electrodeposit is grown the same way as discussed above, e.g., C 2 =+V w /2, R 2 =−V w /2 with limited write time, limited oxidizable metal, or with a resistive barrier between the electrodes (e.g., at the cathode). The resistance remains high after writing as the electrodeposit does not bridge the electrodes. This relatively high resistance state can be differentiated from the full “off” state as the current flow through the device will be altered by the presence of the electrodeposit. One way to detect the presence of a partial electrodeposit is to destructively read the device using an erase pulse, as described above. Alternatively, a write operation can be similarly used to destructively read the state.
FIG. 27 illustrates a three-terminal structure 2700 in accordance with yet another embodiment of the invention. Structure 2700 includes a resistive material such that a current path exists between the electrodeposit and the sense electrode. In this case, a partial electrodeposit is grown as described above, and information is stored as a change in resistance due to the geometric overlap of the electrodeposit and the sense electrode. As illustrated in FIG. 27 , a selected cell 2702 is written via R 2 and C 2 as before and the state (resistance) of the cell is sensed via R 2 and C 2 *. The resistivity of the material between the electrodeposit and the sense electrode must be high enough to prevent low resistance pathways forming between the sense lines.
FIGS. 28 illustrates a lateral programmable structure 2800 , including a first electrode 2802 , a second electrode 2804 , an ion conductor 2806 , and a conducting layer 2808 , formed overlying a substrate 2810 . The underlying conductor 2808 is provided to distribute current and even the lateral electric field as shown in FIG. 28 .
In this example, the electrolyte and its coplanar anode and cathode are formed on a thin high resistance layer that separates the electrolyte from a parallel conductor. The resistive layer parameters are chosen to prevent the electrodes from being shorted together by the conducting layer but also to allow some current to flow to the conductor so that it can be redistributed in the electrolyte. This additional source of current perpendicular to the plane of the electrolyte means that the current is no longer limited by the lateral resistance of the electrolyte and so the electrodeposition can proceed orders of magnitude faster. Also, since the growing electrodeposit is no longer the only source of electrons, the electrodeposition effect may be much more two dimensional, allowing better coverage of the surface.
Note that this approach can also be used with vertical devices, such as structure 2900 , illustrated in FIG. 29 . In this case the electrons will flow through the volume of ion conductor 2902 interposed between a first electrode 2904 and a second electrode 2906 via the parallel high conductivity regions illustrated by the arrows.
FIG. 30 illustrates a structure 3000 , including electrodes 3002 , 3004 , ion conductor 3006 , and a parallel conducting layer 3008 . Electrode 3008 is configured to facilitate a partial electrodeposit which only forms in or on part of the ion conductor. This may be achieved by having parallel conductor 3008 extending only part of the way from the cathode, as illustrated. If this electrode is connected to the cathode (or to a separate supply of electrons), it will facilitate rapid and 2-dimensional growth up to the point on the electrolyte where it ends. Beyond this point, the growth will be fed mostly by electrons from the surface electrodeposit (now the cathode) and hence it will slow down. This way, we can grow only a partial 2-dimensional metal structure. A non-bridging electrodeposit can also be attained in lateral devices or vertical devices with thick electrolyte by using the lowest possible write voltage, i.e., a few mV above the reduction/oxidation potential, to keep the writing field low.
A programmable structure in accordance with the present invention may be used in many applications which would otherwise utilize traditional technologies such as EEPROM, FLASH or DRAM. Advantages provided by the present invention over present memory techniques include, among other things, lower production cost and the ability to use flexible fabrication techniques which are easily adaptable to a variety of applications. The programmable structures of the present invention are especially advantageous in applications where cost is the primary concern, such as smart cards and electronic inventory tags. Also, an ability to form the memory directly on a plastic card is a major advantage in these applications as this is generally not possible with other forms of semiconductor memories.
Further, in accordance with the programmable structures of the present invention, memory elements may be scaled to less than a few square microns in size, the active portion of the device being less than one square micron. This provides a significant advantage over traditional semiconductor technologies in which each device and its associated interconnect can take up several tens of square microns.
Programmable structures and devices and system including the programmable structures described herein are advantageous because the programmable structures require relatively little internal voltage to perform write and erase functions, require relatively little current to perform the write and erase functions, are relatively fast (both write and read operations), require little to no refresh (even for “volatile” memory applications), can be formed in high-density arrays, are relatively inexpensive to manufacture, are robust and shock resistant, and do not require a monocrystalline starting material and can therefore be added to other electronic circuitry.
Although the present invention is set forth herein in the context of the appended drawing figures, it should be appreciated that the invention is not limited to the specific form shown. For example, while the programmable structure is conveniently described above in connection with programmable memory devices, the invention is not so limited; the structure of the present invention may additionally or alternatively be employed as programmable active or passive devices within a microelectronic circuit. Furthermore, although only some of the devices are illustrated as including buffer, barrier, or transistor components, any of these components may be added to the devices of the present invention. Various other modifications, variations, and enhancements in the design and arrangement of the method and apparatus set forth herein, may be made without departing from the spirit and scope of the present invention as set forth in the appended claims.